Renaud Pacalet

According to our database1, Renaud Pacalet authored at least 40 papers between 1997 and 2018.

Collaborative distances:



In proceedings 
PhD thesis 




A Model Compilation Approach for Optimized Implementations of Signal-processing Systems.
Proceedings of the 6th International Conference on Model-Driven Engineering and Software Development, 2018

A Model-Driven Engineering Methodology to Design Parallel and Distributed Embedded Systems.
ACM Trans. Design Autom. Electr. Syst., 2017

Survey on Memory and Devices Disaggregation Solutions for HPC Systems.
Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016

Performance optimizations of integrity checking based on Merkle trees.
Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy, 2015

Hardware-assisted Memory Tracing on New SoCs Embedding FPGA Fabrics.
Proceedings of the 31st Annual Computer Security Applications Conference, 2015

A UML Model-Driven Approach to Efficiently Allocate Complex Communication Schemes.
Proceedings of the Model-Driven Engineering Languages and Systems, 2014

SecBus, a Software/Hardware Architecture for Securing External Memories.
Proceedings of the 2nd IEEE International Conference on Mobile Cloud Computing, 2014

Model-Driven Design of Software Defined Radio Applications Based on UML.
Proceedings of the Embedded Systems Development, From Functional Models to Implementations, 2014

TRESCCA - Trustworthy Embedded Systems for Secure Cloud Computing.
Proceedings of the 2013 International Conference on Availability, Reliability and Security, 2013

Dynamic Power Management for the Iterative Decoding of Turbo Codes.
IEEE Trans. VLSI Syst., 2012

DiplodocusDF, a Domain-Specific Modelling Language for Software Defined Radio Applications.
Proceedings of the 38th Euromicro Conference on Software Engineering and Advanced Applications, 2012

Flexible front-end processing for software defined radio applications using application specific instruction-set processors.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics.
IEEE Trans. Computers, 2010

Formal System-level Design Space Exploration.
Proceedings of the NOTERE 2010, Annual International Conference on New Technologies of Distributed Systems, Touzeur, Tunisia, May 31, 2010

Dynamic Power Management on LDPC Decoders.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Fast Simulation Techniques for Design Space Exploration.
Proceedings of the Objects, Components, Models and Patterns, 47th International Conference, 2009

High-Level System Modeling for Rapid HW/SW Architecture Exploration.
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

Open Platform for Prototyping of Advanced Software Defined Radio and Cognitive Radio Techniques.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

SecBus: Operating System controlled hierarchical page-based memory bus protection.
Proceedings of the Design, Automation and Test in Europe, 2009

Optimum LDPC decoder: a memory architecture problem.
Proceedings of the 46th Design Automation Conference, 2009

Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks.
IEEE Trans. Computers, 2008

Evaluation of ASIPs Design with LISATek.
Proceedings of the Embedded Computer Systems: Architectures, 2008

Silicon-level Solutions to Counteract Passive and Active Attacks.
Proceedings of the Fifth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2008

Flexible Baseband Architectures for Future Wireless Systems.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Application Specific Processors for Multimedia Applications.
Proceedings of the 11th IEEE International Conference on Computational Science and Engineering, 2008

A fast pipelined multi-mode DES architecture operating in IP representation.
Integration, 2007

Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors.
IEEE Design & Test of Computers, 2007

Reconfigurable DSP Architectures for SDR Applications.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Un environnement de conception de systèmes distribués basé sur UML.
Annales des Télécommunications, 2006

A UML-based Environment for System Design Space Exploration.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Using GPU for fast Block-Matching.
Proceedings of the 14th European Signal Processing Conference, 2006

Abstract Application Modeling for System Design Space Exploration.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

The "Backend Duplication" Method.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

SoCs security: a war against side-channels.
Annales des Télécommunications, 2004

CMOS Structures Suitable for Secured Hardware.
Proceedings of the 2004 Design, 2004

Differential Power Analysis Model and Some Results.
Proceedings of the Smart Card Research and Advanced Applications VI, 2004

LUX: A Heterogeneous Parallel Computer Dedicated to Ray Tracing.
Scalable Computing: Practice and Experience, 2000

LUX: An Heterogeneous Function Composition Parallel Computer for Graphics.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

A VLSI Architecture for Image Geometrical Transformations Using an Embedded Core Based Processor.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997