Praveen Raghavan
According to our database1,
Praveen Raghavan
authored at least 131 papers
between 2005 and 2019.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2019
IEEE Trans. Emerg. Top. Comput., 2019
2018
Exploratory design of on-chip power delivery for 14, 10, and 7 nm and beyond FinFET ICs.
Integr., 2018
2017
A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Int. J. Circuit Theory Appl., 2017
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
IR-drop aware Design & technology co-optimization for N5 node with different device and cell height options.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.
Proceedings of the 47th European Solid-State Device Research Conference, 2017
Material selection and device design guidelines for two-dimensional materials based TFETs.
Proceedings of the 47th European Solid-State Device Research Conference, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes.
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Effect of material parameters on two-dimensional materials based TFETs: An energy-delay perspective.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016
Proceedings of the Near Threshold Computing, Technology, Methods and Applications., 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
ACM Trans. Design Autom. Electr. Syst., 2015
Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes.
Microprocess. Microsystems, 2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
STT-MRAM cell design with partial source line planes: improving the trade-off between area and series resistance.
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015
Sub-Threshold SRAM Design in 14 Nm FinFET Technology with Improved Access Time and Leakage Power.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
The defect-centric perspective of device and circuit reliability - From individual defects to circuits.
Proceedings of the 45th European Solid State Device Research Conference, 2015
Comparative analysis of RD and Atomistic trap-based BTI models on SRAM Sense Amplifier.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Characterization and simulation methodology for time-dependent variability in advanced technologies.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform.
IEEE Embed. Syst. Lett., 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Modelling and mitigation of time-zero variability in sub-16nm finfet-based STT-MRAM memories.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.
Proceedings of the 44th European Solid State Device Research Conference, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
Proceedings of the Handbook of Signal Processing Systems, 2013
Design Space Exploration of Distributed Loop Buffer Architectures with Incompatible Loop-Nest Organisations in Embedded Systems.
J. Signal Process. Syst., 2013
Impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based BTI model.
Microprocess. Microsystems, 2013
Enabling Efficient System Configurations for Dynamic Wireless Applications Using System Scenarios.
Int. J. Wirel. Inf. Networks, 2013
Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication.
Int. J. Embed. Real Time Commun. Syst., 2013
Energy impact in the design space exploration of loop buffer schemes in embedded systems.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
An area and energy efficient half-row-paralleled layer LDPC decoder for the 802.11AD standard.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
Impact of partial resistive defects and Bias Temperature Instability on SRAM decoder reliablity.
Proceedings of the 8th International Design and Test Symposium, 2013
Proceedings of the IEEE International Conference on Acoustics, 2013
A processor based multi-standard low-power LDPC engine for multi-Gbps wireless communication.
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013
A C-programmable baseband processor with inner modem implementations for LTE Cat-4/5/7 and Gbps 80MHz 4×4 802.11ac (invited).
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Early exploration for platform architecture instantiation with multi-mode application partitioning.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
DART - a High Level Software-Defined Radio Platform Model for Developing the Run-Time Controller.
J. Signal Process. Syst., 2012
Algorithm-Architecture Co-Optimization of Area-Efficient SDR Baseband for Highly Diversified Digital TV Standards.
Proceedings of the 75th IEEE Vehicular Technology Conference, 2012
Proceedings of the 2012 International Symposium on System on Chip, 2012
Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach.
Proceedings of the 2012 Interconnection Network Architecture, 2012
Impact of Duty Factor, Stress Stimuli, and Gate Drive Strength on Gate Delay Degradation with an Atomistic Trap-Based BTI Model.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Partitioning and Assignment Exploration for Multiple Modes of IEEE 802.11n Modem on Heterogeneous MPSoC Platforms.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Incorporating parameter variations in BTI impact on nano-scale logical gates analysis.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
2011
Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors.
J. Signal Process. Syst., 2011
Enabling efficient system configurations for dynamic wireless baseband engines using system scenarios.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
High level analysis of trade-offs across different partitioning schemes for wireless applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Proceedings of the International SoC Design Conference, 2011
Dart - a high level software-defined radio platform model for developing the run-time controller.
Proceedings of the IEEE International Conference on Acoustics, 2011
An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
2010
J. Signal Process. Syst., 2010
IEEE Signal Process. Mag., 2010
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 5th International ICST Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2010
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010
Proceedings of the Handbook of Signal Processing Systems, 2010
2009
Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2009
ACM Trans. Design Autom. Electr. Syst., 2009
IEEE Trans. Computers, 2009
Microprocess. Microsystems, 2009
Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Des. Autom. Embed. Syst., 2009
Register file exploration for a multi-standard wireless forward error correction ASIP.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009
Proceedings of the Parallel Computing: From Multicores and GPU's to Petascale, 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures.
Integr., 2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
A unified instruction set programmable architecture for multi-standard advanced forward error correction.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
Proceedings of the High Performance Embedded Architectures and Compilers, 2008
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
2007
Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors.
ACM Trans. Design Autom. Electr. Syst., 2007
Int. J. Embed. Syst., 2007
Proceedings of the Embedded Computer Systems: Architectures, 2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Very wide register: an asymmetric register file organization for low power embedded processors.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
Proceedings of the Architecture of Computing Systems, 2007
2006
Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005
Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005