Anu Gupta
Orcid: 0000-0002-6320-556X
According to our database1,
Anu Gupta
authored at least 26 papers
between 2006 and 2024.
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Bibliography
2024
J. Circuits Syst. Comput., February, 2024
2023
AOH-Senti: Aspect-Oriented Hybrid Approach to Sentiment Analysis of Students' Feedback.
SN Comput. Sci., March, 2023
2022
J. King Saud Univ. Comput. Inf. Sci., 2022
Consumer Green Consumption Behavior: A Myth or Reality in the Information Age? A Study Based on Bibliometric Analysis Approach.
Inf. Resour. Manag. J., 2022
2021
A Holistic Framework for Crime Prevention, Response, and Analysis With Emphasis on Women Safety Using Technology and Societal Participation.
IEEE Access, 2021
2019
Constant power consumption design of novel differential logic gate for immunity against differential power analysis.
IET Circuits Devices Syst., 2019
Differential Power Analysis Immune Design of FinFET Based Novel Differential Logic Gate.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Memory-efficient architecture of circle Hough transform and its FPGA implementation for iris localisation.
IET Image Process., 2018
2017
Low-latency median filter core for hardware implementation of 5 × 5 median filtering.
IET Image Process., 2017
2016
A Novel Edge-Map Creation Approach for Highly Accurate Pupil Localization in Unconstrained Infrared Iris Images.
J. Electr. Comput. Eng., 2016
Developing and validating virtualized transactional application of educational institutes using InFraMegh.
Proceedings of the 2016 International Conference on Advances in Computing, 2016
2015
Int. J. Reconfigurable Comput., 2015
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the 2015 IEEE International Conference on Signal and Image Processing Applications, 2015
2014
Proceedings of the 2014 International Conference on Advances in Computing, 2014
2013
Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
2012
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
2010
J. Signal Process. Syst., 2010
2009
Dual channel addition based FFT processor architecture for signal and image processing.
Int. J. High Perform. Syst. Archit., 2009
A Novel Dynamic Current Boosting Technique for Enhancement of Settling Time and Elimination of Slewing of CMOS Amplifiers.
Proceedings of the ARTCom 2009, 2009
Proceedings of the ARTCom 2009, 2009
2008
Design of a High Performance, Low Power, Fully Differential Telescopic Cascode Amplifier using Common-Mode Feedback Circuit.
Proceedings of the Technological Developments in Education and Automation, 2008
2007
An Empirical Investigation of Defect Management in Free/Open Source Software Projects.
Proceedings of the Advances in Computer and Information Sciences and Engineering, 2007
2006
Automation of clock distribution network design for digital integrated circuits using divide and conquer technique.
Integr., 2006