Subhendu Kumar Sahoo
According to our database1,
Subhendu Kumar Sahoo
authored at least 26 papers
between 2008 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
An effective and robust single-image dehazing method based on gamma correction and adaptive Gaussian notch filtering.
J. Supercomput., May, 2024
A new fast and efficient dehazing and defogging algorithm for single remote sensing images.
Signal Process., February, 2024
2021
Tunnel FET-based ultra-lightweight reconfigurable TRNG and PUF design for resource-constrained internet of things.
Int. J. Circuit Theory Appl., 2021
Fast and Efficient Visibility Restoration Technique for Single Image Dehazing and Defogging.
IEEE Access, 2021
2020
Tunnel FET-based ultralow-power and hardware-secure circuit design considering p-i-n forward leakage.
Int. J. Circuit Theory Appl., 2020
Area and power-efficient variable-length fast Fourier transform for MR-OFDM physical layer of IEEE 802.15.4-g.
IET Comput. Digit. Tech., 2020
Low area overhead DPA countermeasure exploiting tunnel transistor-based random number generator.
IET Circuits Devices Syst., 2020
IET Circuits Devices Syst., 2020
A Low Voltage Discriminant Circuit for Pattern Recognition Exploiting the Asymmetrical Characteristics of Tunnel FET.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Tunnel FET ambipolarity-based energy efficient and robust true random number generator against reverse engineering attacks.
IET Circuits Devices Syst., 2019
Multichannel Filters for Wireless Networks: Lookup-Table-Based Efficient Implementation.
IEEE Consumer Electron. Mag., 2019
2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
2017
An area-efficient and low-power 64-point pipeline Fast Fourier Transform for OFDM applications.
Integr., 2017
Lookup Table-Based Low-Power Implementation of Multi-channel Filters for Software Defined Radio.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
Design of a High Performance Carry Generation Circuit for Ternary Full Adder Using CNTFET.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
2015
Implementation of a high speed multiplier for high-performance and low power applications.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
2014
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the 9th International Symposium on Communication Systems, 2014
2010
J. Signal Process. Syst., 2010
2009
Dual channel addition based FFT processor architecture for signal and image processing.
Int. J. High Perform. Syst. Archit., 2009
Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load.
Proceedings of the Second International Conference on Emerging Trends in Engineering & Technology, 2009
A Novel Dynamic Current Boosting Technique for Enhancement of Settling Time and Elimination of Slewing of CMOS Amplifiers.
Proceedings of the ARTCom 2009, 2009
2008
A High-Speed Radix-64 Parallel Multiplier Using a Novel Hardware Implementation Approach for Partial Product Generation Based on Redundant Binary Arithmetic.
Proceedings of the First International Conference on Emerging Trends in Engineering and Technology, 2008