Sharvil Patil

Orcid: 0000-0001-5952-3162

According to our database1, Sharvil Patil authored at least 16 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
22.2 A 700MHZ-BW -164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 3 using Digital Cancellation of DAC Errors.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A 1-MHz-Bandwidth Continuous-Time Delta-Sigma ADC Achieving >90dB SFDR and >80dB Antialiasing Using Reference-Switched Resistive Feedback DACs.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2020
16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
Signal Encoding and Processing in Continuous Time Using a Cascade of Digital Delays.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
Corrections to "Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time".
IEEE J. Solid State Circuits, 2018

2017
A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164-dBFS/Hz NSD.
IEEE J. Solid State Circuits, 2017

2016
A 3-10 fJ/conv-step Error-Shaping Alias-Free Continuous-Time ADC.
IEEE J. Solid State Circuits, 2016

Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time.
IEEE J. Solid State Circuits, 2016

Digital processing of signals produced by voltage-controlled-oscillator-based continuous-time ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Derivative Level-Crossing Sampling.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A 3-10fJ/conv-step 0.0032mm<sup>2</sup> error-shaping alias-free asynchronous ADC.
Proceedings of the Symposium on VLSI Circuits, 2015

Continuous-time hybrid computation with programmable nonlinearities.
Proceedings of the ESSCIRC Conference 2015, 2015

2009
A Novel Dynamic Current Boosting Technique for Enhancement of Settling Time and Elimination of Slewing of CMOS Amplifiers.
Proceedings of the ARTCom 2009, 2009

Improved Implementation of CRL and SCRL Gates for Ultra Low Power.
Proceedings of the ARTCom 2009, 2009


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