Anup Ashok Kedilaya

According to our database, Anup Ashok Kedilaya authored at least 2 papers in 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Metal Stack Exploration for Front- Versus Back- Side Clock and Signal Allocation for Advanced CMOS PPA Improvements.

Nishant Gupta, Sirish Oruganti, S. S. Teja Nibhanupudi, Anup Ashok Kedilaya, Xiuhao Zhang, Jaydeep P. Kulkarni

IEEE Trans. Very Large Scale Integr. Syst., June, 2026

MARU: An ML-Based Framework for Area Estimation from FPGA Resource Usage.

Tarun Kholay, Anup Ashok Kedilaya, Aman Arora, Jaydeep P. Kulkarni, Lizy K. John

Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2026