Sirish Oruganti

According to our database, Sirish Oruganti authored at least 5 papers between 2022 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-Locally-Asynchronous Operation Based on Tunable Replica Circuits.

Sirish Oruganti, Meizhi Wang, Vishnuvardhan V. Iyer, Yipeng Wang, Mengtian Yang, Raghavan Kumar, Sanu K. Mathew, Jaydeep P. Kulkarni

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

Snap-SAT: A One-Shot Energy-Performance-Aware All-Digital Compute-in-Memory Solver for Large-Scale Hard Boolean Satisfiability Problems.

Shanshan Xie, Mengtian Yang, S. Andrew Lanham, Yipeng Wang, Meizhi Wang, Sirish Oruganti, Jaydeep P. Kulkarni

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

Invited: Buried Power Rails and Back-side Power Grids: Prospects and Challenges.

S. S. Teja Nibhanupudi, Sirish Oruganti, Rahul Mathur, Nishant Gupta, Meizhi Wang, Jaydeep P. Kulkarni

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

A GNN Computing-in-Memory Macro and Accelerator with Analog-Digital Hybrid Transformation and CAMenabled Search-reduce.

Yipeng Wang, Shanshan Xie, Jacob N. Rohan, Meizhi Wang, Mengtian Yang, Sirish Oruganti, Jaydeep P. Kulkarni

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022

Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit Blocks.

Meizhi Wang, Sirish Oruganti, Shanshan Xie, Raghavan Kumar, Sanu Mathew, Jaydeep P. Kulkarni

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022