Sirish Oruganti

Orcid: 0000-0002-2895-3159

According to our database1, Sirish Oruganti authored at least 10 papers between 2022 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Metal Stack Exploration for Front- Versus Back- Side Clock and Signal Allocation for Advanced CMOS PPA Improvements.
IEEE Trans. Very Large Scale Integr. Syst., June, 2026

TACC: A 42.9 TOPS/W/mm<sup>2</sup> Ternary/INT/FP LLM Accelerator with Lossless Weight Compression.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025
GSAcc: Accelerate 3D Gaussian Splatting via Depth Speculation and Gaussian-centric Rasterization.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024
Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-Locally-Asynchronous Operation Based on Tunable Replica Circuits.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

Randomization Approaches for Secure SAR ADC Design Resilient Against Power Side-Channel Attacks.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

CILP: An Arbitrary-bit Precision All-digital Compute-in-memory Solver for Integer Linear Programming Problems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
Snap-SAT: A One-Shot Energy-Performance-Aware All-Digital Compute-in-Memory Solver for Large-Scale Hard Boolean Satisfiability Problems.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

Invited: Buried Power Rails and Back-side Power Grids: Prospects and Challenges.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

A GNN Computing-in-Memory Macro and Accelerator with Analog-Digital Hybrid Transformation and CAMenabled Search-reduce.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit Blocks.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022


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