Ardavan Pedram

According to our database, Ardavan Pedram authored at least 27 papers between 2009 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Retrospective: EIE: Efficient Inference Engine on Sparse and Compressed Neural Network.

Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally

CoRR, 2023

2022

Algorithm/architecture solutions to improve beyond uniform quantization in embedded DNN accelerators.

Ardavan Pedram, Ali Shafiee Ardestani, Ling Li, Hamzah Abdel-Aziz, Jun Fang, Joseph Hassoun

J. Syst. Archit., 2022

Griffin: Rethinking Sparse Optimization for Deep Learning Architectures.

Jong Hoon Shin, Ali Shafiee, Ardavan Pedram, Hamzah Abdel-Aziz, Ling Li, Joseph Hassoun

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021

Design Space Exploration of Sparse Accelerators for Deep Neural Networks.

Jong Hoon Shin, Ali Shafiee, Ardavan Pedram, Hamzah Abdel-Aziz, Ling Li, Joseph Hassoun

CoRR, 2021

Rethinking Floating Point Overheads for Mixed Precision DNN Accelerators.

Hamzah Abdel-Aziz, Ali Shafiee, Jong Hoon Shin, Ardavan Pedram, Joseph Hassoun

Proceedings of Machine Learning and Systems 2021, 2021

2020

Campfire: Compressible, Regularization-Free, Structured Sparse Training for Hardware Accelerators.

Noah Gamboa, Kais Kudrolli, Anand Dhoot, Ardavan Pedram

CoRR, 2020

2018

Plasticine: A Reconfigurable Accelerator for Parallel Patterns.

Raghu Prabhakar, Yaqi Zhang, David Koeplinger, Matthew Feldman, Tian Zhao, Stefan Hadjis, Ardavan Pedram, Christos Kozyrakis, Kunle Olukotun

IEEE Micro, 2018

Spatial: a language and compiler for application accelerators.

David Koeplinger, Matthew Feldman, Raghu Prabhakar, Yaqi Zhang, Stefan Hadjis, Ruben Fiszel, Tian Zhao, Luigi Nardi, Ardavan Pedram, Christos Kozyrakis, Kunle Olukotun

Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2018

2017

Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era.

Ardavan Pedram, Stephen Richardson, Mark Horowitz, Sameh Galal, Shahar Kvatinsky

IEEE Des. Test, 2017

Plasticine: A Reconfigurable Architecture For Parallel Paterns.

Raghu Prabhakar, Yaqi Zhang, David Koeplinger, Matthew Feldman, Tian Zhao, Stefan Hadjis, Ardavan Pedram, Christos Kozyrakis, Kunle Olukotun

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

CATERPILLAR: Coarse Grain Reconfigurable Architecture for accelerating the training of Deep Neural Networks.

Yuanfang Li, Ardavan Pedram

Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016

A Systematic Approach to Blocking Convolutional Neural Networks.

Xuan Yang, Jing Pu, Blaine Burton Rister, Nikhil Bhagdikar, Stephen Richardson, Shahar Kvatinsky, Jonathan Ragan-Kelley, Ardavan Pedram, Mark Horowitz

CoRR, 2016

Simulator calibration for accelerator-rich architecture studies.

Mochamad Asri, Ardavan Pedram, Lizy K. John, Andreas Gerstlauer

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Evaluating programmable architectures for imaging and vision applications.

Artem Vasilyev, Nikhil Bhagdikar, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Improving energy efficiency of DRAM by exploiting half page row access.

Heonjae Ha, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

EIE: Efficient Inference Engine on Compressed Deep Neural Network.

Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Deep compression and EIE: Efficient inference engine on compressed deep neural network.

Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark Horowitz, Bill Dally

Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

2014

A Highly Efficient Multicore Floating-Point FFT Architecture Based on Hybrid Linear Algebra/FFT Cores.

Ardavan Pedram, John D. McCalpin, Andreas Gerstlauer

J. Signal Process. Syst., 2014

Algorithm, Architecture, and Floating-Point Unit Codesign of a Matrix Factorization Accelerator.

Ardavan Pedram, Andreas Gerstlauer, Robert A. van de Geijn

IEEE Trans. Computers, 2014

2013

Algorithm/Architecture Codesign of Low Power and High Performance Linear Algebra Compute Fabrics.

Ardavan Pedram

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Transforming a linear algebra core to an FFT accelerator.

Ardavan Pedram, John D. McCalpin, Andreas Gerstlauer

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

Floating Point Architecture Extensions for Optimized Matrix Factorization.

Ardavan Pedram, Andreas Gerstlauer, Robert A. van de Geijn

Proceedings of the 21st IEEE Symposium on Computer Arithmetic, 2013

2012

Codesign Tradeoffs for High-Performance, Low-Power Linear Algebra Architectures.

Ardavan Pedram, Robert A. van de Geijn, Andreas Gerstlauer

IEEE Trans. Computers, 2012

On the Efficiency of Register File versus Broadcast Interconnect for Collective Communications in Data-Parallel Hardware Accelerators.

Ardavan Pedram, Andreas Gerstlauer, Robert A. van de Geijn

Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

A Linear Algebra Core Design for Efficient Level-3 BLAS.

Ardavan Pedram, Syed Zohaib Gilani, Nam Sung Kim, Robert A. van de Geijn, Michael J. Schulte, Andreas Gerstlauer

Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2011

A high-performance, low-power linear algebra core.

Ardavan Pedram, Andreas Gerstlauer, Robert A. van de Geijn

Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

2009

Modeling Cache Effects at the Transaction Level.

Ardavan Pedram, David Craven, Andreas Gerstlauer

Proceedings of the Analysis, 2009