Raghu Prabhakar

According to our database1, Raghu Prabhakar authored at least 20 papers between 2012 and 2023.

Collaborative distances:



In proceedings 
PhD thesis 


On csauthors.net:


Training Large Language Models Efficiently with Sparsity and Dataflow.
CoRR, 2023

Revet: A Language and Compiler for Dataflow Threads.
CoRR, 2023

AI SoC Design Challenges in the Foundation Model Era.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

SambaNova SN10 RDU: A 7nm Dataflow Architecture to Accelerate Software 2.0.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

(CGRA4HPC) 2022 Invited Speaker: Pushing the Boundaries of HPC with the Integration of AI.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

Capstan: A Vector RDA for Sparsity.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

SambaNova SN10 RDU: Accelerating Software 2.0 with Dataflow.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021

Efficient Multiway Hash Join on Reconfigurable Hardware.
Proceedings of the Performance Evaluation and Benchmarking for the Era of Cloud(s), 2019

Scalable interconnects for reconfigurable spatial architectures.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

Design of programmable, energy-efficient reconfigurable accelerators.
PhD thesis, 2018

Plasticine: A Reconfigurable Accelerator for Parallel Patterns.
IEEE Micro, 2018

Spatial: a language and compiler for application accelerators.
Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2018

Plasticine: A Reconfigurable Architecture For Parallel Paterns.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Automatic Generation of Efficient Accelerators for Reconfigurable Hardware.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Generating Configurable Hardware from Parallel Patterns.
Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, 2016

A Study on the Impact of Compiler Optimizations on High-Level Synthesis.
Proceedings of the Languages and Compilers for Parallel Computing, 2012

Towards layout-friendly high-level synthesis.
Proceedings of the International Symposium on Physical Design, 2012

Static and dynamic co-optimizations for blocks mapping in hybrid caches.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

CUDA-For-Clusters: A System for Efficient Execution of CUDA Kernels on Multi-core Clusters.
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012

Compilation and architecture support for customized vector instruction extension.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012