Ali Shafiee

According to our database1, Ali Shafiee authored at least 32 papers between 2010 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2022
Algorithm/architecture solutions to improve beyond uniform quantization in embedded DNN accelerators.
J. Syst. Archit., 2022

MaiT: Leverage Attention Masks for More Efficient Image Transformers.
CoRR, 2022

Griffin: Rethinking Sparse Optimization for Deep Learning Architectures.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021
Design Space Exploration of Sparse Accelerators for Deep Neural Networks.
CoRR, 2021

Rethinking Floating Point Overheads for Mixed Precision DNN Accelerators.
Proceedings of Machine Learning and Systems 2021, 2021

FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-signal DNN Accelerator.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Sparsity-Aware and Re-configurable NPU Architecture for Samsung Flagship Mobile SoC.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

TinyADC: Peripheral Circuit-aware Weight Pruning Framework for Mixed-signal DNN Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Near-Lossless Post-Training Quantization of Deep Neural Networks via a Piecewise Linear Approximation.
CoRR, 2020

Post-training Piecewise Linear Quantization for Deep Neural Networks.
Proceedings of the Computer Vision - ECCV 2020, 2020

2019
ρ: Relaxed Hierarchical ORAM.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
Design and Optimization of Hardware Accelerators for Deep Learning.
PhD thesis, 2018

Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration.
IEEE Micro, 2018

Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration.
CoRR, 2018

An MLP-aware leakage-free memory controller.
Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018

Secure DIMM: Moving ORAM Primitives Closer to Memory.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

VAULT: Reducing Paging Overheads in SGX with Efficient Integrity Verification Structures.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories.
ACM Trans. Archit. Code Optim., 2017

INXS: Bridging the throughput and energy gap for spiking neural networks.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

2016
A Method to Improve Adaptivity of Odd-Even Routing Algorithm in Mesh NoCs.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Understanding and alleviating intra-die and intra-DIMM parameter variation in the memory system.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Enabling technologies for memory compression: Metadata, mapping, and prediction.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015
Avoiding information leakage in the memory controller with fixed service policies.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

2014
Memory bandwidth reservation in the cloud to avoid information leakage in the memory controller.
Proceedings of the HASP 2014, 2014

MemZip: Exploring unconventional benefits from memory compression.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2012
Heterogeneous Interconnect for Low-Power Snoop-Based Chip Multiprocessors.
J. Low Power Electron., 2012

AFRA: A low cost high performance reliable routing for 3D mesh NoCs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
A morphable phase change memory architecture considering frequent zero values.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Application-aware deadlock-free oblivious routing based on extended turn-model.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
Using Partial Tag Comparison in Low-Power Snoop-Based Chip Multiprocessors.
Proceedings of the Computer Architecture, 2010

Helia: Heterogeneous Interconnect for Low Resolution Cache Access in snoop-based chip multiprocessors.
Proceedings of the 28th International Conference on Computer Design, 2010


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