Arunkumar Vijayakumar

According to our database, Arunkumar Vijayakumar authored at least 15 papers between 2011 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2017

Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques.

Arunkumar Vijayakumar, Vinay C. Patil, Daniel E. Holcomb, Christof Paar, Sandip Kundu

IEEE Trans. Inf. Forensics Secur., 2017

Improving reliability of weak PUFs via circuit techniques to enhance mismatch.

Vinay C. Patil, Arunkumar Vijayakumar, Daniel E. Holcomb, Sandip Kundu

Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

2016

An Efficient Method for Clock Skew Scheduling to Reduce Peak Current.

Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

On testing physically unclonable functions for uniqueness.

Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Preventing integrated circuit piracy via custom encoding of hardware instruction set.

Vinay C. Patil, Arunkumar Vijayakumar, Sandip Kundu

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Machine learning resistant strong PUF: Possible or a pipe dream?

Arunkumar Vijayakumar, Vinay C. Patil, Charles B. Prado, Sandip Kundu

Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

On meta-obfuscation of physical layouts to conceal design characteristics.

Vinay C. Patil, Arunkumar Vijayakumar, Sandip Kundu

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

2015

A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics.

Arunkumar Vijayakumar, Sandip Kundu

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

On Maximizing Decoupling Capacitance of Clock-Gated Logic for Robust Power Delivery.

Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Glitch Power Reduction via Clock Skew Scheduling.

Arunkumar Vijayakumar, Sandip Kundu

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

On pattern generation for maximizing IR drop.

Arunkumar Vijayakumar, Vinay C. Patil, Girish Paladugu, Sandip Kundu

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

A Chaotic Ring oscillator based Random Number Generator.

Siva Nishok Dhanuskodi, Arunkumar Vijayakumar, Sandip Kundu

Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

2013

A system-level solution for managing spatial temperature gradients in thinned 3D ICs.

Arunachalam Annamalai, Raghavan Kumar, Arunkumar Vijayakumar, Sandip Kundu

Proceedings of the International Symposium on Quality Electronic Design, 2013

2012

On Design of Low Cost Power Supply Noise Detection Sensor for Microprocessors.

Arunkumar Vijayakumar, Raghavan Kumar, Sandip Kundu

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

2011

Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits.

Sudarshan Srinivasan, Bharath Phanibhushana, Arunkumar Vijayakumar, Sandip Kundu

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011