Raghavan Kumar
Orcid: 0000-0001-7399-1886
According to our database1,
Raghavan Kumar
authored at least 54 papers
between 2011 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%-99.99% Error Coverage in Intel 4 CMOS.
IEEE J. Solid State Circuits, January, 2024
Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-Locally-Asynchronous Operation Based on Tunable Replica Circuits.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
IEEE J. Solid State Circuits, 2023
IACR Cryptol. ePrint Arch., 2023
218Kauth/s, 3nJ/auth SCA/ML-Resistant Privacy-Preserving Mutual Authentication Accelerator with a Crypto-Double-Coupled PUF in 4nm class CMOS.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage in Intel 4 CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
EM SCA White-Box Analysis-Based Reduced Leakage Cell Design and Presilicon Evaluation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit Blocks.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS.
IEEE J. Solid State Circuits, 2021
IEEE J. Solid State Circuits, 2021
Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
A 4900- $\mu$ m<sup>2</sup> 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition.
IEEE J. Solid State Circuits, 2020
A 0.26% BER, 10<sup>28</sup> Challenge-Response Machine-Learning Resistant Strong-PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A 435MHz, 2.5Mbps/W Side-Channel-Attack Resistant Crypto-Processor for Secure RSA-4K Public-Key Encryption in 14nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
INVITED: A 0.26% BER, Machine-Learning Resistant 10<sup>28</sup> Challenge-Response PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS.
IEEE J. Solid State Circuits, 2019
A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2019
A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 4900×m<sup>2</sup> 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019
A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
2015
Side-Channel Assisted Modeling Attacks on Feed-Forward Arbiter PUFs Using Silicon Data.
Proceedings of the Radio Frequency Identification. Security and Privacy Issues, 2015
2014
IACR Cryptol. ePrint Arch., 2014
Precise Fault-Injections using Voltage and Temperature Manipulation for Differential Cryptanalysis.
IACR Cryptol. ePrint Arch., 2014
IACR Cryptol. ePrint Arch., 2014
On Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable Functions.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014
Protecting cryptographic hardware against malicious attacks by nonlinear robust codes.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
2013
Program phase duration prediction and its application to fine-grain power management.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
A system-level solution for managing spatial temperature gradients in thinned 3D ICs.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Litho-aware and low power design of a secure current-based physically unclonable function.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
2012
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
On Design of Temperature Invariant Physically Unclonable Functions Based on Ring Oscillators.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
2011
Design of Unique and Reliable Physically Unclonable Functions Based on Current Starved Inverter Chain.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
On improving reliability of delay based Physically Unclonable Functions under temperature variations.
Proceedings of the HOST 2011, 2011