Sandip Kundu
Orcid: 0000-0001-8221-3824Affiliations:
- University of Massachusetts Amherst, USA
According to our database1,
Sandip Kundu
authored at least 256 papers
between 1988 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2007, "For contributions to design of test methods for integrated circuits".
Timeline
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Online presence:
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on orcid.org
On csauthors.net:
Bibliography
2023
ACM Trans. Archit. Code Optim., June, 2023
EZClone: Improving DNN Model Extraction Attack via Shape Distillation from GPU Execution Profiles.
CoRR, 2023
Proceedings of the 2023 ACM SIGPLAN International Symposium on Memory Management, 2023
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
IEEE Trans. Consumer Electron., 2022
<i>NN-Lock</i>: A Lightweight Authorization to Prevent IP Threats of Deep Learning Models.
ACM J. Emerg. Technol. Comput. Syst., 2022
Reinforcement Learning based Multi-Attribute Slice Admission Control for Next-Generation Networks in a Dynamic Pricing Environment.
Proceedings of the 95th IEEE Vehicular Technology Conference, 2022
Analysis of Fake News Classification for Insight into the Roles of Different Data Types.
Proceedings of the 16th IEEE International Conference on Semantic Computing, 2022
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
A Highly-Efficient Error Detection Technique for General Matrix Multiplication using Tiled Processing on SIMD Architecture.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
Hardening DNNs against Transfer Attacks during Network Compression using Greedy Adversarial Pruning.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
IEEE Trans. Emerg. Top. Comput., 2021
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
MILR: Mathematically Induced Layer Recovery for Plaintext Space Error Correction of CNNs.
Proceedings of the 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2021
2020
Proceedings of the Blockchain Cybersecurity, Trust and Privacy, 2020
MILR: Mathematically Induced Layer Recovery for Plaintext Space Error Correction of CNNs.
CoRR, 2020
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Proceedings of the 28th European Symposium on Artificial Neural Networks, 2020
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020
2019
ACM Trans. Design Autom. Electr. Syst., 2019
J. Hardw. Syst. Secur., 2019
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019
MLPrivacyGuard: Defeating Confidence Information based Model Inversion Attacks on Machine Learning Systems.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Proceedings of the 27th European Symposium on Artificial Neural Networks, 2019
Proceedings of the 2019 IEEE Intl Conf on Dependable, 2019
Remote Configuration of Integrated Circuit Features and Firmware Management via Smart Contract.
Proceedings of the IEEE International Conference on Blockchain, 2019
Proceedings of the 28th IEEE Asian Test Symposium, 2019
2018
On Enhancing Reliability of Weak PUFs via Intelligent Post-Silicon Accelerated Aging.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Proceedings of the 2018 International Symposium on VLSI Design, 2018
Proceedings of the 2018 IEEE/ACM Third International Conference on Internet-of-Things Design and Implementation, 2018
Proceedings of the 2018 IEEE/ACM Third International Conference on Internet-of-Things Design and Implementation, 2018
Adaptive and polymorphic VLIW processor to optimize fault tolerance, energy consumption, and performance.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Defeating Strong PUF Modeling Attack via Adverse Selection of Challenge-Response Pairs.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018
2017
Guest Editorial Securing IoT Hardware: Threat Models and Reliable, Low-Power Design Solutions.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques.
IEEE Trans. Inf. Forensics Secur., 2017
An analytical model for predicting the residual life of an IC and design of residual-life meter.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
Peer pressure on identity: On requirements for disambiguating PUFs in noisy environment.
Proceedings of the 2017 IEEE North Atlantic Test Workshop, 2017
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
A guide to graceful aging: How not to overindulge in post-silicon burn-in for enhancing reliability of weak PUF.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
2016
IEEE Trans. Parallel Distributed Syst., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Managing Test Coverage Uncertainty due to Random Noise in Nano-CMOS: A Case-Study on an SRAM Array.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.
IEEE Trans. Computers, 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Dynamic Reconfiguration vs. DVFS: A Comparative Study on Power Efficiency of Processors.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Efficient Error-Detection and Recovery Mechanisms for Reliability and Resiliency of Multicores.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 25th IEEE North Atlantic Test Workshop, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Preventing integrated circuit piracy via custom encoding of hardware instruction set.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Improving performance per Watt of non-monotonic Multicore Processors via bottleneck-based online program phase classification.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016
Managing Reliability of Integrated Circuits: Lifetime Metering and Design for Healing.
Proceedings of the 25th IEEE Asian Test Symposium, 2016
Modeling Residual Lifetime of an IC Considering Spatial and Inter-Temporal Temperature Variations.
Proceedings of the 25th IEEE Asian Test Symposium, 2016
2015
Guest Editorial: Special Section on Circuit and System Design Methodologies for Emerging Technologies.
IEEE Trans. Emerg. Top. Comput., 2015
ACM Trans. Embed. Comput. Syst., 2015
ACM Trans. Embed. Comput. Syst., 2015
Online mechanism for reliability and power-efficiency management of a dynamically reconfigurable core.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
ACM Trans. Design Autom. Electr. Syst., 2014
ACM Trans. Embed. Comput. Syst., 2014
Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
On Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable Functions.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Reducing Energy per Instruction via Dynamic Resource Allocation and Voltage and Frequency Adaptation in Asymmetric Multicores.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
A runtime support mechanism for fast mode switching of a self-morphing core for power efficiency.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Guest editorial - Design methodologies for nanoelectronic digital and analogue circuits.
IET Circuits Devices Syst., 2013
Game theoretic approach for run-time task scheduling on an multi-processor system on chip.
IET Circuits Devices Syst., 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
A study on polymorphing superscalar processor dynamically to improve power efficiency.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Program phase duration prediction and its application to fine-grain power management.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
A system-level solution for managing spatial temperature gradients in thinned 3D ICs.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Managing test coverage uncertainty due to thermal noise in nano-CMOS: A case-study on an SRAM array.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
An opportunistic prediction-based thread scheduling to maximize throughput/watt in AMPs.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013
2012
Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading in Presence of Gate Delays.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing.
ACM Trans. Design Autom. Electr. Syst., 2012
A Wavelet-Based Spatio-Temporal Heat Dissipation Model for Reordering of Program Phases to Produce Temperature Extremes in a Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays.
IEEE Trans. Computers, 2012
Empirical model for cooperative resizing of processor structures to exploit power-performance efficiency at runtime.
IET Circuits Devices Syst., 2012
J. Electron. Test., 2012
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
On Design of Temperature Invariant Physically Unclonable Functions Based on Ring Oscillators.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
2011
Trans. High Perform. Embed. Archit. Compil., 2011
IEEE Trans. Dependable Secur. Comput., 2011
Proceedings of the 2011 IEEE International Test Conference, 2011
On Screening Reliability Using Lithographic Process Corner Information Gleaned from Tester Measurements.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Design of Unique and Reliable Physically Unclonable Functions Based on Current Starved Inverter Chain.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Lithography Constrained Placement and Post-Placement Layout Optimization for Manufacturability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Maximizing hotspot temperature: Wavelet based modelling of heating and cooling profile of functional workloads.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
On graceful degradation of chip multiprocessors in presence of faults via flexible pooling of critical execution units.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
On graceful degradation of microprocessors in presence of faults via resource banking.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
On improving reliability of delay based Physically Unclonable Functions under temperature variations.
Proceedings of the HOST 2011, 2011
Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Physically unclonable functions for embeded security based on lithographic variation.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
An Online Mechanism to Verify Datapath Execution Using Existing Resources in Chip Multiprocessors.
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
An Efficient Technique for Leakage Current Estimation in Nanoscaled CMOS Circuits Incorporating Self-Loading Effects.
IEEE Trans. Computers, 2010
Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors.
IEEE Trans. Computers, 2010
IEEE Des. Test Comput., 2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor.
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
A study on performance benefits of core morphing in an asymmetric multicore processor.
Proceedings of the 28th International Conference on Computer Design, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
A model to exploit power-performance efficiency in superscalar processors via structure resizing.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Soft Error-Aware Voltage Scaling Technique for Power Minimization in Application-Specific Multiprocessor System-on-Chip.
J. Low Power Electron., 2009
An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 27th International Conference on Computer Design, 2009
Proceedings of the 27th International Conference on Computer Design, 2009
Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines.
Proceedings of the High Performance Embedded Architectures and Compilers, 2009
A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
On process variation tolerant low cost thermal sensor design in 32nm CMOS technology.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
A study on placement of post silicon clock tuning buffers for mitigating impact of process variation.
Proceedings of the Design, Automation and Test in Europe, 2009
Hardware/software co-design architecture for thermal management of chip multiprocessors.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Lithography Simulation Basics and a Study on Impact of Lithographic Process Window on Gate and Path Delays.
J. Low Power Electron., 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
An Automatic Post Silicon Clock Tuning System for Improving System Performance based on Tester Measurements.
Proceedings of the 2008 IEEE International Test Conference, 2008
A Built-in Test and Characterization Method for Circuit Marginality Related Failures.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Modeling and analysis of non-rectangular transistors caused by lithographic distortions.
Proceedings of the 26th International Conference on Computer Design, 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the 17th IEEE Asian Test Symposium, 2008
2007
Guest Editorial: Special Section on "Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems".
IEEE Trans. Very Large Scale Integr. Syst., 2007
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 2007 IEEE International Test Conference, 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 25th International Conference on Computer Design, 2007
Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method.
Proceedings of the 44th Design Automation Conference, 2007
2006
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the 10th European Test Symposium, 2005
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units.
IEEE Trans. Computers, 2004
ITC 2003 Roundtable: Design for Manufacturability.
IEEE Des. Test Comput., 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit.
Proceedings of the 2004 Design, 2004
2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
On path selection for delay fault testing considering operating conditions [logic IC testing].
Proceedings of the 8th European Test Workshop, 2003
Proceedings of the 2003 Design, 2003
Proceedings of the 2003 Design, 2003
2002
Proceedings of the 39th Design Automation Conference, 2002
2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
Proceedings of the 38th Design Automation Conference, 2001
2000
Proceedings of the 5th European Test Workshop, 2000
Performance sensitivity analysis using statistical method and its applications to delay.
Proceedings of ASP-DAC 2000, 2000
1999
Proceedings of the IEEE International Conference On Computer Design, 1999
1998
GateMaker: a transistor to gate level model extractor for simulation, automatic test pattern generation and verification.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
Timing Analysis and Optimization: From Devices to Systems (Abstract of Embedded Tutorial).
Proceedings of the ASP-DAC '98, 1998
1997
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997
Proceedings of the European Design and Test Conference, 1997
1996
1995
On Construction of Non-systematic t-Symmetric Error Correcting/All Unidirectional Error Detecting Codes.
IEICE Trans. Inf. Syst., 1995
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995
1994
An efficient technique for obtaining unate implementation of functions through input encoding.
Integr., 1994
Integr., 1994
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Proceedings of the 31st Conference on Design Automation, 1994
1993
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993
1992
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992
1991
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991
Proceedings of the conference on European design automation, 1991
Proceedings of the conference on European design automation, 1991
1990
IEEE Trans. Computers, 1990
IEEE Des. Test Comput., 1990
1989
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989
1988
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988