Masoumeh Ebrahimi
Orcid: 0000-0001-7877-6712Affiliations:
- Royal Institute of Technology, Sweden
According to our database1,
Masoumeh Ebrahimi
authored at least 110 papers
between 2009 and 2024.
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Bibliography
2024
2023
IEEE Des. Test, December, 2023
Proceedings of the 15th Workshop on General Purpose Processing Using GPU, 2023
2022
IEEE Trans. Parallel Distributed Syst., 2022
IEEE Trans. Emerg. Top. Comput., 2022
Adv. Comput., 2022
Proceedings of the GPGPU@PPoPP 2022: Proceedings of the 14th Workshop on General Purpose Processing Using GPU, 2022
Proceedings of the 2022 IEEE/IFIP Network Operations and Management Symposium, 2022
Proceedings of the IEEE INFOCOM 2022, 2022
Proceedings of the IEEE INFOCOM 2022, 2022
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
Thread-level Parallelism in Fault Simulation of Deep Neural Networks on Multi-Processor Systems.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
2021
IEEE Trans. Computers, 2021
Multiagent Grid Syst., 2021
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Proceedings of the 29th Euromicro International Conference on Parallel, 2021
Proceedings of the 29th Euromicro International Conference on Parallel, 2021
Proceedings of the NANOCOM '21: The Eighth Annual ACM International Conference on Nanoscale Computing and Communication, Virtual Event, Italy, September 7, 2021
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021
On Heterogeneous Transfer Learning for Improved Network Service Performance Prediction.
Proceedings of the IEEE Global Communications Conference, 2021
Proceedings of the 26th IEEE European Test Symposium, 2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Nano Commun. Networks, 2020
Microprocess. Microsystems, 2020
An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
Guest Editorial: Communication-Aware Designs and Methodologies for Reliable and Adaptable On-Chip AI SubSystems and Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
GeFeS: A generalized wrapper feature selection approach for optimizing classification performance.
Comput. Biol. Medicine, 2020
2019
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-Theory Based Analytical Verification.
IEEE Trans. Computers, 2018
First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip.
IEEE Trans. Computers, 2018
A General Methodology on Designing Acyclic Channel Dependency Graphs in Interconnection Networks.
IEEE Micro, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
Minimizing the system impact of router faults by means of reconfiguration and adaptive routing.
Microprocess. Microsystems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
EbDa: A New Theory on Design and Verification of Deadlock-free Interconnection Networks.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017
Proceedings of the 15th IEEE International Conference on Industrial Informatics, 2017
2016
A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs.
IEEE Trans. Computers, 2016
Comput. Electr. Eng., 2016
Proceedings of the Fourth ACM International Workshop on Many-core Embedded Systems, 2016
Proceedings of the International Conference on High Performance Computing & Simulation, 2016
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016
2015
Computing, 2015
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015
An Adaptive, Low Restrictive and Fault Resilient Routing Algorithm for 3D Network-on-Chip.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015
Proceedings of the 8th International Workshop on Network on Chip Architectures, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
2014
J. Supercomput., 2014
Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing.
IEEE Trans. Computers, 2014
Microprocess. Microsystems, 2014
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014
Proceedings of the 3rd International Workshop on Many-core Embedded Systems (MES'2015) held on June 13, 2014
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
2013
A systematic reordering mechanism for on-chip networks using efficient congestion-aware method.
J. Syst. Archit., 2013
Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture.
J. Comput. Syst. Sci., 2013
Fully adaptive routing algorithms and region-based approaches for two-dimensional and three-dimensional networks-on-chip.
IET Comput. Digit. Tech., 2013
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013
Proceedings of the 21st Euromicro International Conference on Parallel, 2013
Proceedings of the 21st Euromicro International Conference on Parallel, 2013
Minimal-path fault-tolerant approach using connection-retaining structure in Networks-on-Chip.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013
Proceedings of the 20th IEEE International Conference on Electronics, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
CARS: congestion-aware request scheduler for network interfaces in NoC-based manycore systems.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
J. Low Power Electron., 2012
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
GLB - Efficient Global Load Balancing method for moderating congestion in on-chip networks.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012
LEAR - A Low-Weight and Highly Adaptive Routing Method for Distributing Congestions in On-chip Networks.
Proceedings of the 20th Euromicro International Conference on Parallel, 2012
HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012
Proceedings of the 3rd IEEE International Conference on Networked Embedded Systems for Every Application, 2012
Proceedings of the 3rd IEEE International Conference on Networked Embedded Systems for Every Application, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model.
Proceedings of the NOCS 2011, 2011
Proceedings of the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications, 2011
Proceedings of the 8th Conference on Computing Frontiers, 2011
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
Memory-efficient logic layer communication platform for 3D-stacked memory-on-processor architectures.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
2010
Proceedings of the 18th Euromicro Conference on Parallel, 2010
A High-Performance Network Interface Architecture for NoCs Using Reorder Buffer Sharing.
Proceedings of the 18th Euromicro Conference on Parallel, 2010
Proceedings of the NOCS 2010, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
Proceedings of the IEEE International Conference on 3D System Integration, 2010
2009
IET Comput. Digit. Tech., 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Proceedings of the Design, Automation and Test in Europe, 2009