Masoumeh Ebrahimi

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

On Heterogeneous Transfer Learning for Improved Network Service Performance Prediction.

[BibT_eX]

[DOI]

Fernando García Sanz

Mohammad Hashem Haghbayan

Andreas Johnsson

Proceedings of the IEEE Global Communications Conference, 2021

Hierarchical Fault Simulation of Deep Neural Networks on Multi-Core Systems.

[BibT_eX]

[DOI]

Masoomeh Karami

Proceedings of the 26th IEEE European Test Symposium, 2021

The Impact of Faults on DNNs: A Case Study.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

BatchSizer: Power-Performance Trade-off for DNN Inference.

[BibT_eX]

[DOI]

Seyed Morteza Nabavinejad

Sherief Reda

Seyed Morteza Nabavinejad

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Traffic-aware performance optimization in Real-time wireless network on chip.

[BibT_eX]

[DOI]

Nano Commun. Networks, 2020

A NoC-based simulator for design and evaluation of deep neural networks.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2020

An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2020

Guest Editorial: Communication-Aware Designs and Methodologies for Reliable and Adaptable On-Chip AI SubSystems and Accelerators.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2020

GeFeS: A generalized wrapper feature selection approach for optimizing classification performance.

[BibT_eX]

[DOI]

Comput. Biol. Medicine, 2020

2019

Efficient Design-for-Test Approach for Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

Testing aware dynamic mapping for path-centric network-on-chip test.

[BibT_eX]

[DOI]

Integr., 2019

NoC-based DNN accelerator: a future design paradigm.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

Online Path-Based Test Method for Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-Theory Based Analytical Verification.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip.

[BibT_eX]

[DOI]

Nacer-Eddine Zergainoh

IEEE Trans. Computers, 2018

A General Methodology on Designing Acyclic Channel Dependency Graphs in Interconnection Networks.

[BibT_eX]

[DOI]

IEEE Micro, 2018

Optimizing dynamic mapping techniques for on-line NoC test.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

A lifetime-aware mapping algorithm to extend MTTF of Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Minimizing the system impact of router faults by means of reconfiguration and adaptive routing.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2017

Non-blocking BIST for continuous reliability monitoring of Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

EbDa: A New Theory on Design and Verification of Deadlock-free Interconnection Networks.

[BibT_eX]

[DOI]

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

A reliable weighted feature selection for auto medical diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Industrial Informatics, 2017

2016

A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Non-Blocking Testing for Network-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Tolerating transient illegal turn faults in NoCs.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2016

Introduction to the Special Section on On-chip parallel and network-based systems.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2016

VisualNoC: A Visualization and Evaluation Environment for Simulation and Mapping.

[BibT_eX]

[DOI]

Proceedings of the Fourth ACM International Workshop on Many-core Embedded Systems, 2016

SEECC: A secure and efficient elliptic curve cryptosystem for E-health applications.

[BibT_eX]

[DOI]

Proceedings of the International Conference on High Performance Computing & Simulation, 2016

CoBRA: Low cost compensation of TSV failures in 3D-NoC.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

2015

In-order delivery approach for 2D and 3D NoCs.

[BibT_eX]

[DOI]

J. Supercomput., 2015

A Light-weight fault-tolerant routing algorithm tolerating faulty links and routers.

[BibT_eX]

[DOI]

Computing, 2015

Fault-resilient routing unit in NoCs.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

A Routing-Level Solution for Fault Detection, Masking, and Tolerance in NoCs.

[BibT_eX]

[DOI]

Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

An Adaptive, Low Restrictive and Fault Resilient Routing Algorithm for 3D Network-on-Chip.

[BibT_eX]

[DOI]

Ronak Salamat

Nader Bagherzadeh

Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Dynamic Application Mapping Algorithm for Wireless Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Automated Power and Latency Management in Heterogeneous 3D NoCs.

[BibT_eX]

[DOI]

Awet Yemane Weldezion

Hannu Tenhunen

Proceedings of the 8th International Workshop on Network on Chip Architectures, 2015

Design of Fault-Tolerant and Reliable Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014

Adaptive load balancing in learning-based approaches for many-core embedded systems.

[BibT_eX]

[DOI]

J. Supercomput., 2014

Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Bi-LCQ: A low-weight clustering-based Q-learning approach for NoCs.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2014

Integration of AES on Heterogeneous Many-Core System.

[BibT_eX]

[DOI]

Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

Improved Route Selection Approaches using Q-learning framework for 2D NoCs.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Workshop on Many-core Embedded Systems (MES'2015) held on June 13, 2014

Exploring Spiking Neural Network on Coarse-Grain Reconfigurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014

Efficient STDP Micro-Architecture for Silicon Spiking Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Parameterized AES-Based Crypto Processor for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Fault tolerant and highly adaptive routing for 2D NoCs.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Rescuing healthy cores against disabled routers.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013

Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip.

[BibT_eX]

[DOI]

Hannu Tenhunen

Masoud Dehyadegari

J. Syst. Archit., 2013

A systematic reordering mechanism for on-chip networks using efficient congestion-aware method.

[BibT_eX]

[DOI]

J. Syst. Archit., 2013

Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture.

[BibT_eX]

[DOI]

J. Comput. Syst. Sci., 2013

Fully adaptive routing algorithms and region-based approaches for two-dimensional and three-dimensional networks-on-chip.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2013

An exploration of heterogeneous systems.

[BibT_eX]

[DOI]

Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

High Performance Fault-Tolerant Routing Algorithm for NoC-Based Many-Core Systems.

[BibT_eX]

[DOI]

Proceedings of the 21st Euromicro International Conference on Parallel, 2013

DyXYZ: Fully Adaptive Routing Algorithm for 3D NoCs.

[BibT_eX]

[DOI]

Proceedings of the 21st Euromicro International Conference on Parallel, 2013

Minimal-path fault-tolerant approach using connection-retaining structure in Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

FPGA implementation of AES-based crypto processor.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Conference on Electronics, 2013

Fault-tolerant routing algorithm for 3D NoC using Hamiltonian path strategy.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

CARS: congestion-aware request scheduler for network interfaces in NoC-based manycore systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

MD: Minimal path-based fault-tolerant routing in on-Chip Networks.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Memory-Efficient On-Chip Network With Adaptive Interfaces.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Adaptive Input-Output Selection Based On-Chip Router Architecture.

[BibT_eX]

[DOI]

J. Low Power Electron., 2012

Adaptive reinforcement learning method for networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

GLB - Efficient Global Load Balancing method for moderating congestion in on-chip networks.

[BibT_eX]

[DOI]

Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

LEAR - A Low-Weight and Highly Adaptive Routing Method for Distributing Congestions in On-chip Networks.

[BibT_eX]

[DOI]

Proceedings of the 20th Euromicro International Conference on Parallel, 2012

HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks.

[BibT_eX]

[DOI]

Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Optimized Q-learning model for distributing traffic in on-Chip Networks.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Conference on Networked Embedded Systems for Every Application, 2012

Dual Congestion Awareness scheme in On-Chip Networks.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Conference on Networked Embedded Systems for Every Application, 2012

MAFA: Adaptive Fault-Tolerant Routing Algorithm for Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

A generic adaptive path-based routing method for MPSoCs.

[BibT_eX]

[DOI]

J. Syst. Archit., 2011

Agent-based on-chip network using efficient selection method.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Efficient congestion-aware selection method for on-chip networks.

[BibT_eX]

[DOI]

Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

High-performance on-chip network platform for memory-on-processor architectures.

[BibT_eX]

[DOI]

Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model.

[BibT_eX]

[DOI]

Proceedings of the NOCS 2011, 2011

Q-learning based congestion-aware routing algorithm for on-chip network.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications, 2011

Cluster-based topologies for 3D stacked architectures.

[BibT_eX]

[DOI]

Proceedings of the 8th Conference on Computing Frontiers, 2011

An adaptive fuzzy logic-based routing algorithm for networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

HIBS - Novel inter-layer bus structure for stacked architectures.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Memory-efficient logic layer communication platform for 3D-stacked memory-on-processor architectures.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010

HAMUM - A Novel Routing Protocol for Unicast and Multicast Traffic in MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 18th Euromicro Conference on Parallel, 2010

A High-Performance Network Interface Architecture for NoCs Using Reorder Buffer Sharing.

[BibT_eX]

[DOI]

Proceedings of the 18th Euromicro Conference on Parallel, 2010

A Low-Latency and Memory-Efficient On-chip Network.

[BibT_eX]

[DOI]

Proceedings of the NOCS 2010, 2010

Performance Analysis of 3D NoCs Partitioning Methods.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

High-Performance TSV Architecture for 3-D ICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Input-Output Selection Based Router for Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Partitioning methods for unicast/multicast traffic in 3D NoC architecture.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

CMIT - A novel cluster-based topology for 3D stacked architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009

Low-distance path-based multicast routing algorithm for network-on-chips.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2009

An Adaptive Unicast/Multicast Routing Algorithm for MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

An efficent dynamic multicast routing protocol for distributing traffic in NOCs.

[BibT_eX]

[DOI]