Ashok Jaiswal

According to our database, Ashok Jaiswal authored at least 14 papers between 2011 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

Source-synchronous I/O Links using Adaptive Interface Training for High Bandwidth Applications

Ashok Jaiswal

PhD thesis, 2014

Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes.

Ashok Jaiswal, Dominik walk, Yuan Fang, Klaus Hofmann

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

A low-jitter clock and data recovery for GDDR5 interface trainings.

Yuan Fang, Jonas Bargon, Ashok Jaiswal, Klaus Hofmann

Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

2013

Deadlock-free generic routing algorithms for 3-dimensional Networks-on-Chip with reduced vertical link density topologies.

Haoyuan Ying, Ashok Jaiswal, Thomas Hollstein, Klaus Hofmann

J. Syst. Archit., 2013

A wide range programmable duty cycle corrector.

Ashok Jaiswal, Yuan Fang, Kashif Nawaz, Klaus Hofmann

Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Low-power signal integrity trainings for multi-clock source-synchronous memory systems.

Yuan Fang, Ashok Jaiswal, Klaus Hofmann

Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Low-power design of hybrid digital impedance calibration for process, voltage, temperature compensations.

Yuan Fang, Uzair Muhammad, Ashok Jaiswal, Klaus Hofmann

Proceedings of the 20th IEEE International Conference on Electronics, 2013

Transmitter equalizer training based on pilot signal and peak detection.

Yuan Fang, Ling Chen, Ashok Jaiswal, Klaus Hofmann

Proceedings of the 20th IEEE International Conference on Electronics, 2013

Adaptive Low-Power Synchronization Technique for Multiple Source-Synchronous Clocks in High-Speed Communication Systems.

Ashok Jaiswal, Yuan Fang, Peter Gregorius, Klaus Hofmann

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Adaptive Equalizer Training for High-Speed Low-Power Communication Systems.

Yuan Fang, Ling Chen, Ashok Jaiswal, Klaus Hofmann, Peter Gregorius

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

Deadlock-free routing algorithms for 3-dimension Networks-on-Chip with reduced vertical channel density topologies.

Haoyuan Ying, Ashok Jaiswal, Klaus Hofmann

Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012

A simulation framework for 3-dimension Networks-on-chip with different vertical channel density configurations.

Haoyuan Ying, Ashok Jaiswal, Mohamed A. Abd El-Ghany, Thomas Hollstein, Klaus Hofmann

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011

Invited paper: Design criteria for dependable System-on-Chip architectures.

Thomas Hollstein, Faizal Arya Samman, Ashok Jaiswal, Haoyuan Ying, Manfred Glesner, Klaus Hofmann

Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

A Fast Congestion-Aware Flow Control Mechanism for ID-Based Networks-on-Chip with Best-Effort Communication.

Haoyuan Ying, Ashok Jaiswal, Thomas Hollstein, Klaus Hofmann

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011