Manfred Glesner

According to our database1, Manfred Glesner authored at least 325 papers between 1986 and 2017.

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Awards

IEEE Fellow

IEEE Fellow 2000, "For contributions to the development of microelectronic system design and education in microelectronics.".

Timeline

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Bibliography

2017
VLSI-SoC: An Enduring Tradition.
Proceedings of the VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things, 2017

2014
High-level abstraction for teaching smart systems design with modular hardware.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

2013
Runtime Contention and Bandwidth-Aware Adaptive Routing Selection Strategies for Networks-on-Chip.
IEEE Trans. Parallel Distrib. Syst., 2013

Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach.
ACM Trans. Embedded Comput. Syst., 2013

Embedded systems design for smart system integration.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

An event-based middleware for the remote management of runtime hardware reconfiguration.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
Erratum to Planar adaptive network-on-chip supporting deadlock-free and efficient tree-based multicast routing method Microprocessors and Microsystems (2012) 449-461.
Microprocessors and Microsystems - Embedded Hardware Design, 2012

Planar adaptive network-on-chip supporting deadlock-free and efficient tree-based multicast routing method.
Microprocessors and Microsystems - Embedded Hardware Design, 2012

A Programmable Look-Up Table-Based Interpolator with Nonuniform Sampling Scheme.
Int. J. Reconfig. Comp., 2012

Hardware acceleration of combined cipher and forward error correction for low-power wireless applications.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Comparative analysis of dynamic task mapping heuristics in heterogeneous NoC-based MPSoCs.
Proceedings of the 2012 International Symposium on System on Chip, 2012

(GECO)2: A graphical tool for the generation of configuration bitstreams for a smart sensor interface based on a Coarse-Grained Dynamically Reconfigurable Architecture.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Implementation and outcomes of FPGA-based system design in Mongolian education.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011
New Theory for Deadlock-Free Multicast Routing in Wormhole-Switched Virtual-Channelless Networks-on-Chip.
IEEE Trans. Parallel Distrib. Syst., 2011

Wormhole cut-through switching: Flit-level messages interleaving for virtual-channelless network-on-chip.
Microprocessors and Microsystems - Embedded Hardware Design, 2011

Exploring dynamic mapping impact on NoC-based MPSoCs performance using a model-based framework.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

On-chip efficient Round-Robin scheduler for high-speed interconnection.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

Design of an autonomous platform for distributed sensing-actuating systems.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

Reconfigurable streaming processor core with interconnected floating-point arithmetic units for multicore adaptive signal processing systems.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Invited paper: Design criteria for dependable System-on-Chip architectures.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

RF energy harvester design with autonomously adaptive impedance matching network based on auxiliary charge-pump rectifier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A Multi-level Reconfigurable Architecture for a Wireless Sensor Node Coprocessing Unit.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Pipelined Floating-Point Architecture for a Phase and Magnitude Detector Based on CORDIC.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Mechanisms and Architecture for the Dynamic Reconfiguration of an Advanced Wireless Sensor Node.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Reconfigurable interconnect infrastructure for multi-FPGA-based adaptive multiprocessing systems.
Proceedings of the 1st International Workshop on Computing in Heterogeneous, 2011

2010
Adaptive and Deadlock-Free Tree-Based Multicast Routing for Networks-on-Chip.
IEEE Trans. VLSI Syst., 2010

Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms.
IJERTCS, 2010

Novel method of chaotic systems evaluation for implementations of encryption algorithms.
Proceedings of the 17th International Conference on Telecommunications, 2010

Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Dynamically Reconfigurable Systems for Wireless Sensor Networks.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

2009
Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management.
VLSI Design, 2009

On the design of reconfigurable multipliers for integer and Galois field multiplication.
Microprocessors and Microsystems - Embedded Hardware Design, 2009

Low-Power Coding for Networks-on-Chip with Virtual Channels.
J. Low Power Electronics, 2009

A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips.
Int. J. Reconfig. Comp., 2009

Providing Memory Management Abstraction for Self-Reconfigurable Video Processing Platforms.
Int. J. Reconfig. Comp., 2009

A Multistep Extrapolated S-Parameter Model for Arbitrary On-Chip Interconnect Structures.
Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009

Generation of Synthetic Floating-Point benchmark circuits.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Towards a unique FPGA-based identification circuit using process variations.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

A flexible floating-point wavelet transform and wavelet packet processor.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Hardware Based Rapid Prototyping.
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

A fast and compact classifier based on sorting in an iteratively expanded input space.
Int. J. Intell. Syst., 2008

A Lifting-Based Discrete Wavelet Transform and Discrete Wavelet Packet Processor with Support for Higher Order Wavelet Filters.
Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008

A Flexible Floating-Point Wavelet Processor.
Proceedings of the 4th IEEE International Conference on Signal Image Technology and Internet Based Systems, 2008

Configurable VLSI Architecture of a General Purpose Lifting-based Wavelet Processor.
Proceedings of the SIGMAP 2008, 2008

Validation of executable application models mapped onto network-on-chip platforms.
Proceedings of the IEEE Third International Symposium on Industrial Embedded Systems, 2008

Enabling self-reconfiguration on a video processing platform.
Proceedings of the IEEE Third International Symposium on Industrial Embedded Systems, 2008

A simplified executable model to evaluate latency and throughput of networks-on-chip.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II.
Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008

A Methodology for Wireless Sensor Network Prototyping with Sophisticated Debugging Support.
Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008

PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Process variations aware robust on-chip bus architecture synthesis for MPSoCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Flexible parallel pipeline network-on-chip based on dynamic packet identity management.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

TinyOS Extensions for a Wireless Sensor Network Node Based on a Dynamically Reconfigurable Processor.
Proceedings of the Distributed Embedded Systems: Design, 2008

High-Speed Configurable VLSI Architecture of a General Purpose Lifting-Based Discrete Wavelet Processor.
Proceedings of the e-Business and Telecommunications - International Conference, 2008

An Actor-Oriented Group Mobility Model for Wireless Ad Hoc Sensor Networks.
Proceedings of the 28th IEEE International Conference on Distributed Computing Systems Workshops (ICDCS 2008 Workshops), 2008

An area-efficient FPGA realisation of a codebook-based image compression method.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

A scalable reconfiguration mechanism for fast dynamic reconfiguration.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Application-specific reconfigurable processors.
Proceedings of the FPL 2008, 2008

High-performance fpga-based floating-point adder with three inputs.
Proceedings of the FPL 2008, 2008

A lifting-based DWT and IDWT processor with multi-context configuration and normalization factor.
Proceedings of the FPL 2008, 2008


Multicast Parallel Pipeline Router Architecture for Network-on-Chip.
Proceedings of the Design, Automation and Test in Europe, 2008

Comparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation.
Proceedings of the Design, Automation and Test in Europe, 2008

An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs.
Proceedings of the Design, Automation and Test in Europe, 2008

Novel approach on lifting-based DWT and IDWT processor with multi-context configuration to support different wavelet filters.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

Impact of circuit nonidealities on the implementation of switched-capacitor resonators.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

A novel leakage-estimation method for input-vector control.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

High-performance floating-point VLSI architecture of lifting-based forward and inverse wavelet transforms.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Low-latency VLSI architecture of a 3-input floating-point adder.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic.
IEEE Trans. VLSI Syst., 2007

On the Evolution of Remote Laboratories for Prototyping Digital Electronic Systems.
IEEE Trans. Industrial Electronics, 2007

Signal Activity Analysis for High-Level Power Estimation in Time-Shared Linear Systems.
J. Low Power Electronics, 2007

Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme).
it - Information Technology, 2007

Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms.
Computers & Electrical Engineering, 2007

Specification of alternative execution semantics of UML sequence diagrams within actor-oriented models.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

A Customizable LEON2-Based VLIW Processor.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

System Level Design of a Dynamically Self-Reconfigurable Image Processing System.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Ein Beitrag zur automatischen Erzeugung dynamisch rekonfigurierbarer Hardwarestrukturen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

Inserting Data Encoding Techniques into NoC-Based Systems.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Reducing the Power Consumption in Networks-on-Chip through Data Coding Schemes.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

An Efficient Fractional-Rate Interpolation Architecture.
Proceedings of the Global Communications Conference, 2007

A Scalable Resampling Architecture.
Proceedings of the Global Communications Conference, 2007

A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor Networks.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

A Power Estimation Model for an FPGA-based Softcore Processor.
Proceedings of the FPL 2007, 2007

Interactive presentation: Executable system-level specification models containing UML-based behavioral patterns.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Exploring Functional Unit Parallelism in Reconfigurable Computing Platforms.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

A Concept for a Profile-based Dynamic Reconfiguration Mechanism.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Adaptable Image Processing System based on FPGA Modular Multi Kernel Instantiations.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

A CMOS Compatible Charge Recovery Logic Family for Low Supply Voltages.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Eine Scheduling Heuristik zur Minimierung der Verlustleistung.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

An Actor-Oriented Model-Based Design Flow for Systems-on-Chip.
Proceedings of the Dagstuhl-Workshop MBEES: Modellbasierte Entwicklung eingebetteter Systeme II, 2006

An Efficient Hardware Implementation of a Self-Adaptable Equalizer for WCDMA Downlink UMTS Standard.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Reduction of Crosstalk Pessimism using Tendency Graph Approach.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Multitasking Support for Dynamically Reconfig Urable Systems.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Applying Communication Patterns to Actor-Oriented Models.
Proceedings of the Forum on specification and Design Languages, 2006

A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Towards an Automated Design of Application-specific Reconfigurable Logic.
Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006

Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint.
Proceedings of the 43rd Design Automation Conference, 2006

A metric for the energy-efficiency of dynamically reconfigurable systems.
Proceedings of the ARCS 2006, 2006

Implementation of Realtime and Highspeed Phase Detector on FPGA.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

Design Concepts for a Dynamically ReconfigurableWireless Sensor Node.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

2005
An FPGA implementation of the AES-Rijndael in OCB/ECB modes of operation.
Microelectronics Journal, 2005

On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Non-linear addressing scheme for a lookup-based transformation function in a reconfigurable noise generator.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques.
Proceedings of the Embedded Computer Systems: Architectures, 2005

Modeling and Prototyping of Communication Systems Using Java: A Case Study.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

Analysis and Architectural Study of a Hybrid ASIC/Configurable State Machine Model.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

Experiences on Actor-oriented Design of Reconfigurable Systems.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

Advanced On-Chip Communication Architectures and Routing Methods for Systems-on-Chip.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

Proxy-Based Integration of Reconfigurable Hardware Within Simulation Environments: Improving E-Learning Experience in Microelectronics.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

Functional modeling techniques for a wireless LAN OFDM transceiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

High level hardware/software communication estimation in shared memory architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A linear model for high-level delay estimation in VDSM on-chip interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Buffer-Architecture Exploration for Routers in a Hierarchical Network-on-Chip.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

HW/SW design and realization of a size-reconfigurable DCT accelerator.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

Deadlock-free routing and component placement for irregular mesh-based networks-on-chip.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Abstrakte Modellierung der Eigenschaften von nanoelektronischen CNT-Elementen in SystemC.
Proceedings of the INFORMATIK 2005, 2005

Eine weiterentwickelte quasi-statische adiabatische Logikfamilie.
Proceedings of the INFORMATIK 2005, 2005

A State-Serial Viterbi Decoder Architecture for Digital Radio on FPGA.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Optimal FFT Architecture Selection for OFDM Receivers on FPGA.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

On-Chip Communication Topology Synthesis for a Shared Memory Architecture.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

CONAN - A Design Exploration Framework for Reliable Nano-Electronics.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

Prozessorintegration und Speicheranbindung dynamisch rekonfigurierbarer Funktionseinheiten.
Proceedings of the 18th International Conference on Architecture of Computing Systems, 2005

2004
Um Framework de Apoio à Colaboração no Projeto Distribuído de Sistemas Integrados.
RITA, 2004

A power-constrained design strategy for CMOS tuned low noise amplifiers.
Microelectronics Reliability, 2004

Lookup-based Remote Laboratory for FPGA Digital Design Prototyping.
Proceedings of the e-learning and Virtual and Remote Laboratories, 2004

A switch architecture and signal synchronization for GALS system-on-chips.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Accurate capture of timing parameters in inductively-coupled on-chip interconnects.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Rapid Prototyping of an Integrated Testing and Debugging Unit.
Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004), 2004

Moment-Based Estimation of Switching Activity for Correlated Distributions.
Proceedings of the Integrated Circuit and System Design, 2004

On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects.
Proceedings of the Integrated Circuit and System Design, 2004

An Asynchronous Switch Implmentation for Systems-on-a-Chip.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

Flexible Overhead Processing Architectures for G.709 Optical Transport Networks.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Design of a reconfigurable AES encryption/decryption engine for mobile terminals.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Dynamic power optimization of the trace-back process for the Viterbi algorithm.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals.
Proceedings of the Field Programmable Logic and Application, 2004

The XPP Architecture and Its Co-simulation Within the Simulink Environment.
Proceedings of the Field Programmable Logic and Application, 2004

IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter.
Proceedings of the Field Programmable Logic and Application, 2004

On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing.
Proceedings of the First Conference on Computing Frontiers, 2004

Reconfigurable platforms for ubiquitous computing.
Proceedings of the First Conference on Computing Frontiers, 2004

Integration dynamisch rekonfigurierbarer Funktionseinheiten in Prozessoren.
Proceedings of the ARCS 2004, 2004

2003
On the Rapid Prototyping of Equalizers for OFDM Systems.
Design Autom. for Emb. Sys., 2003

Hardware-Assisted Signal Activity Analysis for Power Estimation in Rapid Prototyped Systems.
Design Autom. for Emb. Sys., 2003

Transition Activity Estimation for General Correlated Data Distributions.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

Exploring the Capabilities of Reconfigurable Hardware for OFDM-based WLANs.
Proceedings of the IFIP VLSI-SoC 2003, 2003

An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

A hierarchical generic approach for on-chip communication, testing and debugging of SoCs.
Proceedings of the IFIP VLSI-SoC 2003, 2003

A Versatile Cellular Neural Circuit Based on a Multi-nested Approach: Functional Capabilities and Applications.
Proceedings of the IFIP VLSI-SoC 2003, 2003

High Performance of an AES-Rijndael ASIC working in OCB/ECB Modes of Operation.
Proceedings of the IFIP VLSI-SoC 2003, 2003

An Integrated Model Bridging the Gap between Technology and Economy.
Proceedings of the IFIP VLSI-SoC 2003, 2003

The requirement for flexibility in IP-based designs increasesHardware Evaluation of Low Power Communication Mechanisms for Transport-Triggered Architectures.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

Emulation of Analog Components for the Rapid Prototyping of Wireless Baseband Systems.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

Switching Activity Estimation in Non-linear Architectures.
Proceedings of the Integrated Circuit and System Design, 2003

Reducing Authoring Costs of Online Training in Microelectronics Design by Reusing Design Documentation Content.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Compact image compression using simplicial and ART neural systems with mixed signal implementations.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A multi-path high speed Viterbi decoder.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

A linearization technique for radio frequency CMOS Gilbert-type mixers.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

A low-IF architecture for dual-standard GSM/UMTS fully integrated receivers.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

Moment-Based Power Estimation in Very Deep Submicron Technologies.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Reconfiguration requirements for high speed wireless communication systems.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Arbitrary function approximation in HDLs with application to the N-body problem.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

A granularity-based classification model for systems-on-a-chip.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Supporting Consistency Control between Functional and Structural Views in Interface-based Design Models.
Proceedings of the Forum on specification and Design Languages, 2003

Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues.
Proceedings of the 2003 Design, 2003

2002
The simplicial neural cell and its mixed-signal circuit implementation: an efficient neural-network architecture for intelligent signal processing in portable multimedia applications.
IEEE Trans. Neural Networks, 2002

On the Rapid Prototyping of Equalizers for OFDM Systems.
Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 2002

Prototyping of a High Performance Generic Viterbi Decoder.
Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 2002

Power Estimation Based on Transition Activity Analysis with an Architecture Precise Rapid Prototyping System.
Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 2002

Rapid Prototyping of FPGA Based Floating Point DSP Systems.
Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 2002

Efficient estimation of signal transition activity in MAC architectures.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

A discrete algorithm for the regularization of hierarchical VHDL-AMS models.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Design of an efficient OFDM burst synchronization scheme.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Power reduction techniques for an OFDM burst synchronization core.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension.
Proceedings of the Field-Programmable Logic and Applications, 2002

A Framework for Teaching (Re)Configurable Architectures in Student Projects.
Proceedings of the Field-Programmable Logic and Applications, 2002

Fly - A Modifiable Hardware Compiler.
Proceedings of the Field-Programmable Logic and Applications, 2002

Estimation of Power Consumption in Encoded Data Buses.
Proceedings of the 2002 Design, 2002

Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments.
Proceedings of the 2002 Design, 2002

Regularization of hierarchical VHDL-AMS models using bipartite graphs.
Proceedings of the 39th Design Automation Conference, 2002

2001
A Parallel Dynamically Reconfigurable Architecture Designed for Flexible Application-Tailored Hardware/Software Systems in Future Mobile Communication.
The Journal of Supercomputing, 2001

Lower bound on the accuracy of the CORDIC-based frequency offset compensation in burst oriented OFDM systems.
Proceedings of the 54th IEEE Vehicular Technology Conference, 2001

Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems.
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001

Concept of a Joint University/Industry Course for Mixed-Signal System-On-Chip Design.
Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

Transformierende Synthese zur Verlustleistungsreduktion mittels Partitionierung.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001

A low power sinusoidal clock.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Distributed Collaborative Design over Cave2 Framework.
Proceedings of the SOC Design Methodologies, 2001

Finite-precision analysis of an OFDM burst synchronization scheme.
Proceedings of the Global Telecommunications Conference, 2001

Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures.
Proceedings of the Field-Programmable Logic and Applications, 2001

2000
A flexible and approximate computing approach for time-frequency distributions.
IEEE Trans. Signal Processing, 2000

Flexible architectures for DCT of variable-length targeting shape-adaptive transform.
IEEE Trans. Circuits Syst. Video Techn., 2000

Design methodology of application specific integrated circuits for mechatronic systems.
Microprocessors and Microsystems - Embedded Hardware Design, 2000

Eine flexible Simulationsumgebung für System-On-Chip Design (A Flexible Simulation Environment for System-On-Chip Design).
it+ti - Informationstechnik und Technische Informatik, 2000

Synthese von Kommunikationsstrukturen und architekturgenaues Rapid-Prototyping eingebetteter Echtzeitsysteme (Communication Synthesis and Architecture-Precise Rapid Prototyping of Embedded systems with Hard Real-Time Constraints).
it+ti - Informationstechnik und Technische Informatik, 2000

Automated Communication Synthesis for Architecture-Precise Rapid Prototyping of Real-Time Embedded Systems.
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000

Hardware Accelerated Estimation of Multiplexer-Introduced Loss for MPEG-4 Data Streams.
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000

Simulation and Rapid Prototyping of Flexible Systems-on-a-Chip for Future Mobile Communication Applications.
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000

Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

IP-based Application Mapping Techniques for Dynamically Reconfigurable Hardware Architectures.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

Communication Performance Estimation and Communication Synthesis for Architecture-precise Prototyping of Real-time Embedded Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000

Estimation of Multiplexer-Introduced Loss for MPEG-4 Data Streams Connected to (R)CBR Channels.
Proceedings of the Fifth IEEE Symposium on Computers and Communications (ISCC 2000), 2000

Configurable VLSI-architectures for both standard DCT and shape-adaptive DCT in future MPEG-4 circuit implementations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Rotating stall analysis using signal-adapted filter bank and Cohen's time-frequency distributions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

An efficient filter bank architecture for the cross-term reduced processing of discrete time-frequency distributions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Direct Bayes Point Machines.
Proceedings of the Seventeenth International Conference on Machine Learning (ICML 2000), Stanford University, Stanford, CA, USA, June 29, 2000

Computing discrete time-frequency distributions using principal component filter bank.
Proceedings of the IEEE International Conference on Acoustics, 2000

Field Programmable Communication Emulation and Optimization for Embedded System Design.
Proceedings of the Field-Programmable Logic and Applications, 2000

DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications.
Proceedings of the Field-Programmable Logic and Applications, 2000

Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

A dynamically reconfigurable system-on-a-chip architecture for future mobile digital signal processing.
Proceedings of the 10th European Signal Processing Conference, 2000

An Open VHDL-AMS Simulation Framework.
Proceedings of the 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, 2000

1999
Fuzzy segmented image coding using orthonormal bases and derivative chain coding.
Pattern Recognition, 1999

Mikrosystemtechnik.
it+ti - Informationstechnik und Technische Informatik, 1999

Design and Test of MEMs.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Communication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems.
Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999

Object-oriented Specification Approach for Synthesis of Hardware-/Software Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 1999

Accelerated training of support vector machines.
Proceedings of the International Joint Conference Neural Networks, 1999

Support vector approaches for engine knock detection.
Proceedings of the International Joint Conference Neural Networks, 1999

On the variance reduction of neural networks-experimental results for an automotive application.
Proceedings of the International Joint Conference Neural Networks, 1999

Perceptrons revisited: the addition of a non-monotone recursion greatly enhances their representation and classification properties.
Proceedings of the International Joint Conference Neural Networks, 1999

ILP-Based Board-Level Routing of Multi-Terminal Nets for Prototyping Reconfigurable Interconnect.
Proceedings of the VLSI: Systems on a Chip, 1999

A new flexible architecture for variable length DCT targeting shape-adaptive transform.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

A data-driven scheme for the approximated computing of alias-free generalized discrete time-frequency distributions.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

MPEG-4 PC - Authoring and Playing of MPEG-4 Content for Local and Broadcast Applications.
Proceedings of the Multimedia Applications, Services and Techniques, 1999

Parallel Hardware Compilation in Complex Hardware/Software Systems based on High-Level Code Transformations.
Proceedings of the Architektur von Rechensystemen, Systemarchitektur auf dem Weg ins 3. Jahrtausend: Neue Strukturen, Konzepte, Verfahren und Bewertungsmethoden, 1999

1998
Rapid Prototyping of Real-Time Information Processing Units for Mechatronic Systems.
Real-Time Systems, 1998

Development and Implementation of a Neural Knock Detector Using Constructive Learning Methods.
International Journal of Uncertainty, Fuzziness and Knowledge-Based Systems, 1998

A client/server application as an example for MPEG-4 systems.
Computer Communications, 1998

Rapid Prototyping of a Co-Processor Based Engine Knock Detection System.
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998

Run-Time Monitoring of Communication Activities in a Rapid Prototyping Environment.
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998

Pruning and Regularization Techniques for Feed Forward Nets Applied on a Real World Data Base.
Proceedings of the International ICSC / IFAC Symposium on Neural Computation (NC 1998), 1998

Constructive Learning of a Sub-Feature Detector Network by Means of Prediction Risk Estimation.
Proceedings of the International ICSC / IFAC Symposium on Neural Computation (NC 1998), 1998

A Reconfigurable Hardware-Monitor for Communication Analysis in Distributed Real-Time Systems.
Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998

Flexible Multiplexing in MPEG-4 Systems.
Proceedings of the Interactive Distributed Multimedia Systems and Telecommunication Services, 1998

An FPFA Implementation of a Magnetic Bearing Controller for Mechatronic Applications.
Proceedings of the Field-Programmable Logic and Applications, 1998

Perspectives of Reconfigurable Computing in Research, Industry and Education.
Proceedings of the Field-Programmable Logic and Applications, 1998

Sound signature analysis using time-frequency signal processing: Application to active stall avoidance in axial compressors.
Proceedings of the 9th European Signal Processing Conference, 1998

Advanced Hardware and Software Architectures for Computational Intelligence: Application to a Real World Problem.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

Generation of Interconnect Topologies for Communication Synthesis.
Proceedings of the 1998 Design, 1998

HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

1997
An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions.
ACM Trans. Design Autom. Electr. Syst., 1997

Determination of target volumes for three-dimensional radiotherapy of cancer patients with a fuzzy system.
Fuzzy Sets and Systems, 1997

Advanced data preprocessing using fuzzy clustering techniques.
Fuzzy Sets and Systems, 1997

Hardware in-the-loop simulation-a rapid prototyping approach for designing mechatronics systems.
Proceedings of the Proceedings 8th IEEE International Workshop on Rapid System Prototyping: Shortening the Path from Specification to Prototype, 1997

Rapid prototyping of communication architectures.
Proceedings of the Proceedings 8th IEEE International Workshop on Rapid System Prototyping: Shortening the Path from Specification to Prototype, 1997

An Object-Oriented Client/Server Architecture for Video-on-Demand Applications.
Proceedings of the Interactive Distributed Multimedia Systems and Telecommunication Services, 1997

A prototyping environment for fuzzy controllers.
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

Automatic transfer of parametric FEM models into CAD-layout formats for top-down design of microsystems.
Proceedings of the European Design and Test Conference, 1997

Generation of the HDL-A-model of a micromembrane from its finite-element-description.
Proceedings of the European Design and Test Conference, 1997

CAD and Foundries for Microsystems.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Computer-aided design of fuzzy systems based on generic VHDL specifications.
IEEE Trans. Fuzzy Systems, 1996

Rapid-Prototyping of a CAN-Bus Controller: A Case Study.
Proceedings of the Seventh IEEE International Workshop on Rapid System Prototyping (RSP '96), 1996

An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions.
Proceedings of the 9th International Symposium on System Synthesis, 1996

Bus-Based Communication Synthesis on System-Level.
Proceedings of the 9th International Symposium on System Synthesis, 1996

Image coding with fuzzy region-growing segmentation.
Proceedings of the Proceedings 1996 International Conference on Image Processing, 1996

CAPpartx: Computer Aided Prototyping Partitioning for Xilinx FPGAs, a Hierarchical Partitioning Tool for Rapid Prototyping.
Proceedings of the Field-Programmable Logic, 1996

Applied design and analysis of microsystems.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Visual inspection in industrial manufacturing.
IEEE Micro, 1995

Fuzzy neural networks: between functional equivalence and applicability.
Int. J. Neural Syst., 1995

An alternative approach for generation of membership functions and fuzzy rules based on radial and cubic basis function networks.
Int. J. Approx. Reasoning, 1995

Multidimensional defuzzification - fast algorithms for the determination of crisp characteristic subsets.
Proceedings of the 1995 ACM symposium on applied computing, 1995

A sub Bayesian nearest prototype neural network with fuzzy interpretability for diagnosis problems.
Proceedings of the 1995 ACM symposium on applied computing, 1995

Comparison of a heuristic method with a genetic algorithm for generation of compact rule based classifiers.
Proceedings of the 1995 ACM symposium on applied computing, 1995

Rapid prototyping in microsystems development.
Proceedings of the Sixth IEEE International Workshop on Rapid System Prototyping (RSP '95), 1995

Advanced Method for Industry Related Education with an FPGA Design Self-Learning Kit.
Proceedings of the Field-Programmable Logic and Applications, 5th International Workshop, 1995

Prototype Generation of Application-Specific Embedded Controllers for Microsystems.
Proceedings of the Field-Programmable Logic and Applications, 5th International Workshop, 1995

Multiway netlist partitioning onto FPGA-based board architecture.
Proceedings of the Proceedings EURO-DAC'95, 1995

1994
DECADE - fast centroid approximation defuzzification for real time fuzzy control applications.
Proceedings of the 1994 ACM Symposium on Applied Computing, 1994

Fuzzy neural fusion techniques for industrial applications.
Proceedings of the 1994 ACM Symposium on Applied Computing, 1994

Automatic generation of a fuzzy classification system using fuzzy clustering methods.
Proceedings of the 1994 ACM Symposium on Applied Computing, 1994

MCEMS Toolbox - A Hardware-in-the-Loop Simulation Environment for Mechatronic Systems.
Proceedings of the MASCOTS '94, Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation On Computer and Telecommunication Systems, January 31, 1994

A Design Methodology for the Conceptual Design of Application Specific Digital Processors in Mechatronic Systems.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

Rapid-Prototyping von anwendungsspezifischen Fuzzy Controllern mit Field Programmable Gate Arrays.
Proceedings of the Fuzzy Logik, 1994

Generating compilers for generated datapaths.
Proceedings of the Proceedings EURO-DAC'94, 1994

Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations.
Proceedings of the Proceedings EURO-DAC'94, 1994

Systematic Methods for Multivariate Data Visualization and Numerical Assessment of Class Separability and Overlap in Automated Visual Industrial Quality Control.
Proceedings of the British Machine Vision Conference, 1994

1993
Estimating lower hardware bounds in high-level synthesis.
Proceedings of the VLSI 93, 1993

Approximative Synthese von Fuzzy - Controllern.
Proceedings of the Fuzzy Logic, 1993

Echtzeit Fahrbahnzustandserkennung mit Fuzzy-Neuronalen Netzen.
Proceedings of the Fuzzy Logic, 1993

High-level synthesis transformations for programmable architectures.
Proceedings of the European Design Automation Conference 1993, 1993

Synthesis of complex VHDL operators.
Proceedings of the European Design Automation Conference 1993, 1993

Real-Time System Prototyping Based on a Heterogeneous Multi-Processor Environment.
Proceedings of the Fifth Euromicro Workshop on Real-Time Systems, 1993

1992
High Level Synthesis in an FPL-Based Computer Aided Prototyping Environment.
Proceedings of the Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31, 1992

Application-specific microelectronics for mechatronic systems.
Proceedings of the conference on European design automation, 1992

High-level synthesis in a rapid-prototype environment for mechatronic systems.
Proceedings of the conference on European design automation, 1992

1991
A VLSI System Design for the Control of High Performance Combustion Engines.
Proceedings of the VLSI 91, 1991

RAMSES-a rapid prototyping environment for embedded control applications.
Proceedings of the Second International Workshop on Rapid System Prototyping, 1991

A New Approach for Designing Fault-Tolerant Array Processors.
Proceedings of the Fault-Tolerant Computing Systems, Tests, Diagnosis, 1991

A new approach to timing driven partitioning of combinational logic.
Proceedings of the First Great Lakes Symposium on VLSI, 1991

A CAD tool for designing large, fault-tolerant VLSI arrays.
Proceedings of the First Great Lakes Symposium on VLSI, 1991

HADES-high-level architecture development and exploration system.
Proceedings of the First Great Lakes Symposium on VLSI, 1991

An approach for multilevel logic cell optimization in module generators.
Proceedings of the First Great Lakes Symposium on VLSI, 1991

A VLSI implementation of a state variable filter algorithm.
Proceedings of the First Great Lakes Symposium on VLSI, 1991

1990
Evaluation of state-of-the-art neural network customized hardware.
Neurocomputing, 1990

Timing Driven Partitioning of Combinational Logic.
Proceedings of the Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, 1990

Handwritten pattern recognition with a binary associative memory.
Proceedings of the IJCNN 1990, 1990

1988
Entwurf eines systolischen Arrays in Wafer Scale Technik für die digitale Signalverarbeitung.
Proceedings of the GI, 1988

A Defect-Tolerant and Fully Testable PLA.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987
The ALGIC Silicon Compiler System: Implementation, Design Experience and Results.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986
Statische und dynamische CMOS-Schaltungstechniken im Vergleich.
it - Informationstechnik, 1986

SCAT - a new statistical timing verifier in a silicon compiler system.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986


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