Thomas Hollstein

According to our database1, Thomas Hollstein authored at least 62 papers between 1992 and 2020.

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Bibliography

2020
An Efficient FPGA-based Architecture for Contractive Autoencoders.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019
Detecting and Mitigating Low-and-Slow DoS Attacks in NoC-based MPSoCs.
Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019

2018
A Distributed DoS Detection Scheme for NoC-based MPSoCs.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

Software-Level TMR Approach for On-Board Data Processing in Space Applications.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

2017
Comprehensive performance and robustness analysis of 2D turn models for network-on-chips.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Automated area and coverage optimization of minimal latency checkers.
Proceedings of the 22nd IEEE European Test Symposium, 2017

From online fault detection to fault management in Network-on-Chips: A ground-up approach.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

2016
Holistic Approach for Fault-Tolerant Network-on-Chip based Many-Core Systems.
CoRR, 2016

Foreword.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

SoCDep<sup>2</sup>: A framework for dependable task deployment on many-core systems under mixed-criticality constraints.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Logic-based implementation of fault-tolerant routing in 3D network-on-chips.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

Practicing start-up culture in teaching embedded systems.
Proceedings of the 11th European Workshop on Microelectronics Education, 2016

2015
Automated minimization of concurrent online checkers for Network-on-Chips.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Mixed-criticality NoC partitioning based on the NoCDepend dependability technique.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

NoCDepend: A Flexible and Scalable Dependability Technique for 3D Networks-on-Chip.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014
A hardware/software co-design reconfigurable Network-on-Chip FPGA emulation method.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Dynamic quadrant partitioning adaptive routing algorithm for irregular reduced vertical link density topology 3-Dimensional Network-on-Chips.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014

Motivation-driven learning processes at the example of embedded systems.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

A modular 6LoWPAN-based wireless sensor body area network for health-monitoring applications.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2014

2013
Runtime Contention and Bandwidth-Aware Adaptive Routing Selection Strategies for Networks-on-Chip.
IEEE Trans. Parallel Distributed Syst., 2013

Deadlock-free generic routing algorithms for 3-dimensional Networks-on-Chip with reduced vertical link density topologies.
J. Syst. Archit., 2013

GSNoC - The comprehensive design platform for 3-dimensional Networks-on-Chip based many core embedded systems.
Proceedings of the International Conference on High Performance Computing & Simulation, 2013

Fast and optimized task allocation method for low vertical link density 3-dimensional networks-on-chip based many core systems.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Erratum to Planar adaptive network-on-chip supporting deadlock-free and efficient tree-based multicast routing method Microprocessors and Microsystems (2012) 449-461.
Microprocess. Microsystems, 2012

Planar adaptive network-on-chip supporting deadlock-free and efficient tree-based multicast routing method.
Microprocess. Microsystems, 2012

Communication-centric high level synthesis metrics for low vertical channel density 3-dimensional Networks-on-Chip.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Design methodology for fault-tolerant heterogeneous MPSoC under real-time constraints.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

A genetic algorithm based optimization method for low vertical link density 3-dimensional Networks-on-Chip many core systems.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

A simulation framework for 3-dimension Networks-on-chip with different vertical channel density configurations.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
New Theory for Deadlock-Free Multicast Routing in Wormhole-Switched Virtual-Channelless Networks-on-Chip.
IEEE Trans. Parallel Distributed Syst., 2011

Wormhole cut-through switching: Flit-level messages interleaving for virtual-channelless network-on-chip.
Microprocess. Microsystems, 2011

Invited paper: Design criteria for dependable System-on-Chip architectures.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Contention aware scheduling for NoC-based real-time systems.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

A Fast Congestion-Aware Flow Control Mechanism for ID-Based Networks-on-Chip with Best-Effort Communication.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
Adaptive and Deadlock-Free Tree-Based Multicast Routing for Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2010

2009
Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management.
VLSI Design, 2009

2008
Hardware Based Rapid Prototyping.
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

Flexible parallel pipeline network-on-chip based on dynamic packet identity management.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Multicast Parallel Pipeline Router Architecture for Network-on-Chip.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms.
Comput. Electr. Eng., 2007

2005
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques.
Proceedings of the Embedded Computer Systems: Architectures, 2005

Advanced On-Chip Communication Architectures and Routing Methods for Systems-on-Chip.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

Buffer-Architecture Exploration for Routers in a Hierarchical Network-on-Chip.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Deadlock-free routing and component placement for irregular mesh-based networks-on-chip.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004
Rapid Prototyping of an Integrated Testing and Debugging Unit.
Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004), 2004

An Asynchronous Switch Implmentation for Systems-on-a-Chip.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

Reconfigurable platforms for ubiquitous computing.
Proceedings of the First Conference on Computing Frontiers, 2004

2003
Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

A hierarchical generic approach for on-chip communication, testing and debugging of SoCs.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
Integrated Design and Test Generation Under Internet Based Environment MOSCITO.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

2001
Concept of a Joint University/Industry Course for Mixed-Signal System-On-Chip Design.
Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

1999
Object-oriented Specification Approach for Synthesis of Hardware-/Software Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 1999

1998
From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms.
Proceedings of the 1998 Design, 1998

HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

1997
A prototyping environment for fuzzy controllers.
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

1996
Computer-aided design of fuzzy systems based on generic VHDL specifications.
IEEE Trans. Fuzzy Syst., 1996

1995
Advanced Method for Industry Related Education with an FPGA Design Self-Learning Kit.
Proceedings of the Field-Programmable Logic and Applications, 5th International Workshop, 1995

1994
Rapid-Prototyping von anwendungsspezifischen Fuzzy Controllern mit Field Programmable Gate Arrays.
Proceedings of the Fuzzy Logik, 1994

1992
High-level synthesis in a rapid-prototype environment for mechatronic systems.
Proceedings of the conference on European design automation, 1992


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