Ashutosh Dhar

Orcid: 0000-0001-6376-3142

According to our database1, Ashutosh Dhar authored at least 11 papers between 2015 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs.
IEEE Trans. Computers, 2022

2021
Reconfigurable and heterogeneous architectures for efficient computing
PhD thesis, 2021

WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

Graviton: A Reconfigurable Memory-Compute Fabric for Data Intensive Applications.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021

2020
Leveraging Dynamic Partial Reconfiguration with Scalable ILP Based Task Scheduling.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

FReaC Cache: Folded-logic Reconfigurable Computing in the Last Level Cache.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

2019
Near-Memory and In-Storage FPGA Acceleration for Emerging Cognitive Computing Workloads.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving.
Proceedings of the International Conference on Computer-Aided Design, 2019

2018
Application-Transparent Near-Memory Processing Architecture with Memory Channel Network.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

2017
Efficient GPGPU Computing with Cross-Core Resource Sharing and Core Reconfiguration.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

2015
A scalable and high-density FPGA architecture with multi-level phase change memory.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015


  Loading...