Thomas Röwer
This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.
Bibliography
2024
14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2018
Application-Transparent Near-Memory Processing Architecture with Memory Channel Network.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
2017
Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
2012
A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012
2001
2000
PhD thesis, 2000
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1999
Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
1998
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998