Cong Hao

According to our database1, Cong Hao authored at least 28 papers between 2012 and 2019.

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Bibliography

2019
SkyNet: a Hardware-Efficient Method for Object Detection and Tracking on Embedded Systems.
CoRR, 2019

SkyNet: A Champion Model for DAC-SDC on Low Power Object Detection.
CoRR, 2019

A Bi-Directional Co-Design Approach to Enable Deep Learning on IoT Devices.
CoRR, 2019

FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge.
CoRR, 2019

T-DLA: An Open-source Deep Learning Accelerator for Ternarized DNN Models on Embedded FPGA.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

µL2Q: An Ultra-Low Loss Quantization Method for DNN Compression.
Proceedings of the International Joint Conference on Neural Networks, 2019

Cloud-DNN: An Open Framework for Mapping DNN Models to Cloud FPGAs.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
TSV Assignment of Thermal and Wirelength Optimization for 3D-IC Routing.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Economical Smart Home Scheduling by Cuckoo Search optimization via Levy Flight.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Triangle Counting and Truss Decomposition using FPGA.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

The Sixth Visual Object Tracking VOT2018 Challenge Results.
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Proceedings of the Computer Vision - ECCV 2018 Workshops, 2018

2017
Interconnection Allocation Between Functional Units and Registers in High-Level Synthesis.
IEEE Trans. VLSI Syst., 2017

A Unified Scheduling Approach for Power and Resource Optimization With Multiple Vdd or/and Vth in High-Level Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

An Efficient Multi-Level Algorithm for 3D-IC TSV Assignment.
IEICE Transactions, 2017

3D-IC signal TSV assignment for thermal and wirelength optimization.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Application of on-line machine learning in optimization algorithms: A case study for local search.
Proceedings of the 2017 9th Computer Science and Electronic Engineering Conference, 2017

2016
Leakage-Power-Aware Scheduling With Dual-Threshold Voltage Design.
IEEE Trans. VLSI Syst., 2016

An efficient algorithm for 3D-IC TSV assignment.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Power-efficient partitioning and cluster generation design for application-specific Network-on-Chip.
Proceedings of the International SoC Design Conference, 2016

2015
Primal-dual method based simultaneous functional unit and register binding.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Leakage Power Aware Scheduling in High-Level Synthesis.
IEICE Transactions, 2014

2013
Network simplex method based Multiple Voltage Scheduling in Power-efficient High-level synthesis.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Power and resource aware scheduling with multiple voltages.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Timing and resource constrained leakage power aware scheduling in high-level synthesis.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Interconnection allocation between functional units and registers in High-Level Synthesis.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
Port assignment for interconnect reduction in high-level synthesis.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012


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