Aswin Raghav Krishna

According to our database1, Aswin Raghav Krishna authored at least 9 papers between 2011 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
Design and Validation for FPGA Trust under Hardware Trojan Attacks.
IEEE Trans. Multi Scale Comput. Syst., 2016

2015
MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2014
Hardware trojan attacks in FPGA devices: threat analysis and effective counter measures.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2013
ScanPUF: Robust ultralow-overhead PUF using scan chain.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
SCARE: Side-Channel Analysis Based Reverse Engineering for Post-Silicon Validation.
Proceedings of the 25th International Conference on VLSI Design, 2012

Software exploitable hardware Trojans in embedded processor.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
Sequential hardware Trojan: Side-channel aware design and placement.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

High-temperature (>500°C) reconfigurable computing using silicon carbide NEMS switches.
Proceedings of the Design, Automation and Test in Europe, 2011

MECCA: A Robust Low-Overhead PUF Using Embedded Memory Array.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011


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