Francis G. Wolff

According to our database1, Francis G. Wolff authored at least 52 papers between 1998 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Explainable Neural Network Recognition of Handwritten Characters.
Proceedings of the 13th IEEE Annual Computing and Communication Workshop and Conference, 2023

2020
Design Space Exploration Driven by Lifetime Concerns due to Electromigration.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

2019
Methodology for Tradeoffs between Performance and Lifetimes of Integrated Circuits.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2015
Efficient Hardware Implementations of Binary-to-BCD Conversion Schemes for Decimal Multiplication.
J. Circuits Syst. Comput., 2015

A robust authentication methodology using physically unclonable functions in DRAM arrays.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Knowledge-Guided Methodology for Third-Party Soft IP Analysis.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Cross-correlation of specification and RTL for soft IP analysis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Ontology-guided Conceptual Analysis of Design Specifications.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis.
IEEE Trans. Computers, 2013

Knowledge-Guided Methodology for Specification Analysis.
Proceedings of the 25th IEEE International Conference on Tools with Artificial Intelligence, 2013

NEFCIS: Neuro-fuzzy Concept Based Inference System for Specification Mining.
Proceedings of the 25th IEEE International Conference on Tools with Artificial Intelligence, 2013

2012
An efficient elliptic curve cryptography processor using addition chains with high information entropy.
Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012

2011
Smoothing delay jitter in networked control systems.
J. Embed. Comput., 2011

Fast binary/decimal adder/subtractor with a novel correction-free BCD addition.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Fast and compact binary-to-BCD conversion circuits for decimal multiplication.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

High-temperature (>500°C) reconfigurable computing using silicon carbide NEMS switches.
Proceedings of the Design, Automation and Test in Europe, 2011

An analysis of efficient formulas for elliptic curve point addition over binary extension fields.
Proceedings of the 45st Annual Conference on Information Sciences and Systems, 2011

2010
Trustworthy computing in a multi-core system using distributed scheduling.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach.
Proceedings of the HOST 2010, 2010

A supply-demand model based scalable energy management system for improved energy utilization efficiency.
Proceedings of the International Green Computing Conference 2010, 2010

Embedded system protection from software corruption.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

Process reliability based trojans through NBTI and HCI effects.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

System level self-healing for parametric yield and reliability improvement under power bound.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

2009
Exploiting Semiconductor Properties for Hardware Trojans
CoRR, 2009

Hardware Trojan by Hot Carrier Injection
CoRR, 2009

An Improved Algorithm to Smooth Delay Jitter in Cyber-Physical Systems.
Proceedings of the International Conference on Scalable Computing and Communications / Eighth International Conference on Embedded Computing, 2009

SRAM cell design using tri-state devices for SEU protection.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Efficient architectures for elliptic curve cryptography processors for RFID.
Proceedings of the 27th International Conference on Computer Design, 2009

Dynamic Evaluation of Hardware Trust.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009

Avoiding Delay Jitter in Cyber-Physical Systems Using One Way Delay Variations Model.
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

MERO: A Statistical Approach for Hardware Trojan Detection.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2009

An Adaptable Task Manager for Reconfigurable Architecture Kernels.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

2008
SRAM Cell Design Protected from SEU Upsets.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

An Embedded Flash Memory Vault for Software Trojan Protection.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
A Self Test Program Design Technique for Embedded DSP Cores.
J. Electron. Test., 2006

FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A Dynamic Reconfigurable Fabric for Platform SoCs.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Soft delay error analysis in logic circuits.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A Large Scale Adaptable Multiplier for Cryptographic Applications.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

2005
Node sensitivity analysis for soft errors in CMOS logic.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories.
Proceedings of the 2005 Design, 2005

2004
Soft Delay Error Effects in CMOS Combinational Circuits.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Test Compression and Hardware Decompression for Scan-Based SoCs.
Proceedings of the 2004 Design, 2004

Designing Self Test Programs for Embedded DSP Cores.
Proceedings of the 2004 Design, 2004

2003
A Technique for High Ratio LZW Compression.
Proceedings of the 2003 Design, 2003

2002
Multiscan-Based Test Compression and Hardware Decompression Using LZ77.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

1999
Estimation of Software Reliability by Stratified Sampling.
ACM Trans. Softw. Eng. Methodol., 1999

Using codesign techniques to support analog functionality.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
An experiment with WWW interactive learning in university education.
Comput. Educ., 1998


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