Xinmu Wang

According to our database1, Xinmu Wang authored at least 25 papers between 2011 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2021
SOMA: Security Evaluation of Obfuscation Methods via Attack Sequencing.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

2020
A formal model for proving hardware timing properties and identifying timing channels.
Integr., 2020

Content Delivery for High-Speed Railway via Integrated Terrestrial-Satellite Networks.
Proceedings of the 2020 IEEE Wireless Communications and Networking Conference, 2020

Overlay Coded Multicast for Edge Caching in 5G-Satellite Integrated Networks.
Proceedings of the 2020 IEEE Wireless Communications and Networking Conference, 2020

2019
Theorem proof based gate level information flow tracking for hardware security verification.
Comput. Secur., 2019

Blockchain-Based Secure and Trustworthy Internet of Things in SDN-Enabled 5G-VANETs.
IEEE Access, 2019

Optimizing Adaptive Coding and Modulation for Satellite Network with ML-based CSI Prediction.
Proceedings of the 2019 IEEE Wireless Communications and Networking Conference, 2019

Cooperative Network-Coded Multicast for Layered Content Delivery in D2D-Enhanced HetNets.
Proceedings of the 2019 IEEE Symposium on Computers and Communications, 2019

Network Coded Cooperative Multicast in Integrated Terrestrial-Satellite Networks.
Proceedings of the 2019 IEEE Symposium on Computers and Communications, 2019

Leveraging Unspecified Functionality in Obfuscated Hardware for Trojan and Fault Attacks.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019

2018
Hardware Trojan attacks in embedded memory.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Property specific information flow analysis for hardware security verification.
Proceedings of the International Conference on Computer-Aided Design, 2018

Security Path Verification Through Joint Information Flow Analysis.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Golden-Free Hardware Trojan Detection with High Sensitivity Under Process Noise.
J. Electron. Test., 2017

2015
SACCI: Scan-Based Characterization Through Clock Phase Sweep for Counterfeit Chip Detection.
IEEE Trans. Very Large Scale Integr. Syst., 2015

IIPS: Infrastructure IP for Secure SoC Design.
IEEE Trans. Computers, 2015

2013
Role of power grid in side channel attack and power-grid-aware secure design.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Improving IC Security Against Trojan Attacks Through Integration of Security Monitors.
IEEE Des. Test Comput., 2012

SCARE: Side-Channel Analysis Based Reverse Engineering for Post-Silicon Validation.
Proceedings of the 25th International Conference on VLSI Design, 2012

Software exploitable hardware Trojans in embedded processor.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
NEMTronics: Symbiotic integration of nanoelectronic and nanomechanical devices for energy-efficient adaptive computing.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Sequential hardware Trojan: Side-channel aware design and placement.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

TeSR: A robust Temporal Self-Referencing approach for Hardware Trojan detection.
Proceedings of the HOST 2011, 2011

High-temperature (>500°C) reconfigurable computing using silicon carbide NEMS switches.
Proceedings of the Design, Automation and Test in Europe, 2011

MECCA: A Robust Low-Overhead PUF Using Embedded Memory Array.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011


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