Athon Zanikopoulos

According to our database1, Athon Zanikopoulos authored at least 10 papers between 2005 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2013
An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2011
A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS.
IEEE J. Solid State Circuits, 2011

A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2007
Design of the Basic Building Block of a High-Speed Flexible and Modular Pipelined ADC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Analog Calibration of Mismatches in an Open-Loop Track-and-Hold Circuit for Time-Interleaved ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Digital post-correction of front-end track-and-hold circuits in ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Power Optimization for Pipelined ADCs with Open-Loop Residue Amplifiers.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
A flexible ADC approach for mixed-signal SoC platforms.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Smart AD and DA converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Digital self-correction of time-interleaved ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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