Georgi I. Radulov
According to our database1,
Georgi I. Radulov
authored at least 30 papers
between 2005 and 2024.
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Bibliography
2024
32.6 A 76-to-81GHz Direct-Digital 7b 14GS/s Double-Balanced I/Q Mixing-DAC Radar-Waveform Synthesizer.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2022
IEEE J. Solid State Circuits, 2022
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Time Interleaved ADC Mismatch Error Correction Technique in I/Q Digital Beamforming Receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS.
Proceedings of the 47th ESSCIRC 2021, 2021
2020
Analysis of the Inter-Stage Signal Leakage in Wide BW Low OSR and High DR CT MASH ΔΣM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the European Conference on Circuit Theory and Design, 2020
A 0.037mm<sup>2</sup> 1GSps 12b self-calibrated 40nm CMOS DAC cell with SFDR>60dB up to 200MHz and IM3 < - 60dB up to 350MHz.
Proceedings of the European Conference on Circuit Theory and Design, 2020
A novel analysis of the beam squinting in wideband phased array digital I/Q transmitters.
Proceedings of the European Conference on Circuit Theory and Design, 2020
2018
A 2 GHz 0.98 mW 4-bit SAR-Based Quantizer with ELD Compensation in an UWB CT ΣΔ Modulator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
IEEE J. Solid State Circuits, 2016
A digital calibration technique for wide-band CT MASH ΣΔ ADCs with relaxed filter requirements.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz.
IEEE Trans. Very Large Scale Integr. Syst., 2015
A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
A novel timing-error based approach for high speed highly linear Mixing-DAC architectures.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
2012
Systematic analysis of the impact of mixing locality on Mixing-DAC linearity for multicarrier GSM.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2009
2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
Brownian-Bridge-Based Statistical Analysis of the DAC INL Caused by Current Mismatch.
IEEE Trans. Circuits Syst. II Express Briefs, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A start-up calibration method for generic current-steering D/A converters with optimal area solution.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005