Georgi I. Radulov

According to our database1, Georgi I. Radulov authored at least 23 papers between 2005 and 2020.

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Bibliography

2020
Analysis of the Inter-Stage Signal Leakage in Wide BW Low OSR and High DR CT MASH ΔΣM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Novel Baseband Analog Beamforming through Resistive DACs and Sigma Delta Modulators.
Proceedings of the European Conference on Circuit Theory and Design, 2020

A 0.037mm<sup>2</sup> 1GSps 12b self-calibrated 40nm CMOS DAC cell with SFDR>60dB up to 200MHz and IM3 < - 60dB up to 350MHz.
Proceedings of the European Conference on Circuit Theory and Design, 2020

A novel analysis of the beam squinting in wideband phased array digital I/Q transmitters.
Proceedings of the European Conference on Circuit Theory and Design, 2020

2018
A 2 GHz 0.98 mW 4-bit SAR-Based Quantizer with ELD Compensation in an UWB CT ΣΔ Modulator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
A Wideband RF Mixing-DAC Achieving IMD < -82 dBc Up to 1.9 GHz.
IEEE J. Solid State Circuits, 2016

A digital calibration technique for wide-band CT MASH ΣΔ ADCs with relaxed filter requirements.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2015

9.6 A 5.3GHz 16b 1.75GS/S wideband RF Mixing-DAC achieving IMD<-82dBc up to 1.9GHz.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
A novel timing-error based approach for high speed highly linear Mixing-DAC architectures.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
A novel output transformer based highly linear RF-DAC architecture.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012
Systematic analysis of the impact of mixing locality on Mixing-DAC linearity for multicarrier GSM.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A novel temperature and disturbance insensitive DAC calibration method.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2009
Smart Front-Ends, from Vision to Design.
IEICE Trans. Electron., 2009

2008
A flexible 12-bit self-calibrated quad-core current-steering DAC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Brownian-Bridge-Based Statistical Analysis of the DAC INL Caused by Current Mismatch.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Parallel current-steering D/A Converters for Flexibility and Smartness.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
A binary-to-thermometer decoder with built-in redundancy for improved DAC yield.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Smart AD and DA converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A start-up calibration method for generic current-steering D/A converters with optimal area solution.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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