Gerard van der Weide

According to our database1, Gerard van der Weide authored at least 13 papers between 2004 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2013
An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2011
A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS.
IEEE J. Solid State Circuits, 2011

A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2009
A 65 nm CMOS Inductorless Triple Band Group WiMedia UWB PHY.
IEEE J. Solid State Circuits, 2009

A 65nm CMOS inductorless triple-band-group WiMedia UWB PHY.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
A 0.6-to-10GHz Receiver Front-End in 45nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
A 56 mW Continuous-Time Quadrature Cascaded ΣΔ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band.
IEEE J. Solid State Circuits, 2007

Design of MOS transconductors with low noise and low harmonic distortion for minimum current consumption.
Integr., 2007

A Broadband Receive Chain in 65nm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 56mW CT Quadrature Cascaded ΣΔ Modulator with 77dB DR in a Near Zero-IF 20MHz Band.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A WiMedia-Compliant UWB Transceiver in 65nm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005
A low power implementation for the transmit path of a UWB transceiver.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Design of high-performance asynchronous sigma delta modulators with a binary quantizer with hysteresis.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004


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