Zhaolin Li

According to our database1, Zhaolin Li authored at least 36 papers between 2004 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Study on Green Construction Evaluation of Highway in Seasonal Frozen Zone.
J. Inf. Technol. Res., 2021

Interactive Quantum Classifier Inspired by Quantum Open System Theory.
Proceedings of the International Joint Conference on Neural Networks, 2021

Quantum Correlation Revealed by Bell State for Classification Tasks.
Proceedings of the International Joint Conference on Neural Networks, 2021

2020
ERA-LSTM: An Efficient ReRAM-Based Architecture for Long Short-Term Memory.
IEEE Trans. Parallel Distributed Syst., 2020

Oligopoly newsvendor competition with reference effects.
Oper. Res. Lett., 2020

An efficient object detection framework with modified dense connections for small objects optimizations.
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020

2019
An area- and energy-efficient hybrid architecture for floating-point FFT computations.
Microprocess. Microsystems, 2019

2017
A Spatial and Temporal Locality-Aware Adaptive Cache Design With Network Optimization for Tiled Many-Core Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2016
A pipelined area-efficient and high-speed reconfigurable processor for floating-point FFT/IFFT and DCT/IDCT computations.
Microelectron. J., 2016

Temperature-aware multi-application mapping on network-on-chip based many-core systems.
Microprocess. Microsystems, 2016

A hybrid SDC/SDF architecture for area and power minimization of floating-point FFT computations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Temperature-aware task scheduling heuristics on Network-on-Chips.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

STLAC: A spatial and temporal locality-aware cache and network-on-chip codesign for tiled many-core systems.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
A Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Schedule refinement for homogeneous multi-core processors in the presence of manufacturing-caused heterogeneity.
Frontiers Inf. Technol. Electron. Eng., 2015

Mapping of Embedded Applications on Hybrid Networks-on-Chip with Multiple Switching Mechanisms.
IEEE Embed. Syst. Lett., 2015

Designing Multi-Attribute Procurement Mechanisms for Assortment Planning.
Decis. Sci., 2015

Scheduling stream programs with improving arithmetic unit usage on NoC-based VLIW multi-core architectures.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2014
Compiler-Assisted Leakage- and Temperature- Aware Instruction-Level VLIW Scheduling.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A High-Utilization Scheduling Schemeof Stream Programs on ClusteredVLIW Stream Architectures.
IEEE Trans. Parallel Distributed Syst., 2014

2013
Energy-efficient stream task scheduling scheme for embedded multimedia applications on multi-issued stream architectures.
J. Syst. Archit., 2013

Compiler-assisted leakage energy optimization of media applications on stream architectures.
Proceedings of the International Symposium on Quality Electronic Design, 2013

A power-efficient network-on-chip for multi-core stream processors.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Implementation of H.264 intra-frame encoding on clustered stream architectures.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
On jointly optimising the changes of seasonable goods and inventory replenishment.
Int. J. Syst. Sci., 2012

Acquisition and Disclosure of Operational Information.
Decis. Sci., 2012

Equity-Based Incentives and Supply Chain Buy-Back Contracts.
Decis. Sci., 2012

GNSS/INS State Estimation for Multi-Robot Systems Based on Embedded Multi-core Stream Architecture.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Low Power Schedule Algorithm for Embedded Multimedia Applications Basing on Imagine-L Processor.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

2011
An energy efficiency task scheduling algorithm for streaming applications on multiprocessor SoC.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
On determining optimal fleet size and vehicle transfer policy for a car rental company.
Comput. Oper. Res., 2010

2007
Managing a Single-Product Assemble-to-Order System with Technology Innovations.
Manag. Sci., 2007

Design of A Fully Pipelined Single-Precision Multiply-Add-Fused Unit.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Design of A Double-Precision Floating- Point Multiply-Add-Fused Unit with Consideration of Data Dependence.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Optimized design of a double-precision floating-point multiply-add-dused unit for data dependence.
Proceedings of the 25th International Conference on Computer Design, 2007

2004
Efficiency in shortage reduction when using a more expensive common component.
Comput. Oper. Res., 2004


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