Baris Esen

Orcid: 0000-0002-5540-4374

Affiliations:
  • Katholieke Universiteit Leuven, Belgium


According to our database1, Baris Esen authored at least 14 papers between 2014 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
Machine Learning-based Defect Coverage Boosting of Analog Circuits under Measurement Variations.
ACM Trans. Design Autom. Electr. Syst., 2020

2018
An Automated Low-Cost Analog and Mixed-Signal DfT Method Using Testing Diodes.
IEEE Des. Test, 2018

ADAGE: Automatic DfT-Assisted Generation of Test Stimuli for Mixed- Signal Integrated Circuits.
IEEE Des. Test, 2018

Methodology Towards Sub-ppm Testing of Analog and Mixed-Signal ICs for Cyber-Physical Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Non-intrusive detection of defects in mixed-signal integrated circuits using light activation.
Proceedings of the IEEE International Test Conference, 2017

Automatic testing of analog ICs for latent defects using topology modification.
Proceedings of the 22nd IEEE European Test Symposium, 2017

A very low cost and highly parallel DfT method for analog and mixed-signal circuits.
Proceedings of the 22nd IEEE European Test Symposium, 2017

2016
Automatic generation of test infrastructures for analog integrated circuits by controllability and observability co-optimization.
Integr., 2016

Effective DC fault models and testing approach for open defects in analog circuits.
Proceedings of the 2016 IEEE International Test Conference, 2016

Analog fault coverage improvement using final-test dynamic part average testing.
Proceedings of the 2016 IEEE International Test Conference, 2016

Automatic test signal generation for mixed-signal integrated circuits using circuit partitioning and interval analysis.
Proceedings of the 2016 IEEE International Test Conference, 2016

2015
Automated testing of mixed-signal integrated circuits by topology modification.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Automatic generation of autonomous built-in observability structures for analog circuits.
Proceedings of the 20th IEEE European Test Symposium, 2015

2014
Design and test of analog circuits towards sub-ppm level.
Proceedings of the 2014 International Test Conference, 2014


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