Bart Desoete

According to our database¹, Bart Desoete authored at least 3 papers between 2000 and 2006.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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Article

PhD thesis

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Bibliography

2006

A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor.

[BibT_eX]

[DOI]

Yogesh Singh Chauhan

Costin Anghel

François Krummenacher

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2002

A reversible carry-look-ahead adder using control gates.

[BibT_eX]

[DOI]

Bart Desoete

Alexis De Vos

Integr., 2002

2000

Design of Reversible Logic Circuits by Means of Control Gates.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design, 2000

Bart Desoete

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Bibliography

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