Yogesh Singh Chauhan

According to our database1, Yogesh Singh Chauhan authored at least 38 papers between 2006 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

On csauthors.net:

Bibliography

2022
Impact of NCFET Technology on Eliminating the Cooling Cost and Boosting the Efficiency of Google TPU.
IEEE Trans. Computers, 2022

2021
PROTON: Post-Synthesis Ferroelectric Thickness Optimization for NCFET Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

On the Resiliency of NCFET Circuits Against Voltage Over-Scaling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Improved modeling of flicker noise including velocity saturation effect in FinFETs and experimental validation.
Microelectron. J., 2021

Study of multi-domain switching dynamics in negative capacitance FET using SPICE model.
Microelectron. J., 2021

Impact of NCFET on Neural Network Accelerators.
IEEE Access, 2021

A Low Noise Power Amplifier MMIC to Mitigate Co-Site Interference in 5G Front End Modules.
IEEE Access, 2021

Transistor Self-Heating: The Rising Challenge for Semiconductor Testing.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

2020
Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Associative processing using negative capacitance FDSOI transistor for pattern recognition.
Microelectron. J., 2020

Power Side-Channel Attacks in Negative Capacitance Transistor.
IEEE Micro, 2020

Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET).
CoRR, 2020

Impact of Radiation on Negative Capacitance FinFET.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Cell Library Characterization using Machine Learning for Design Technology Co-Optimization.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

NCFET to Rescue Technology Scaling: Opportunities and Challenges.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Neuromorphic Circuits on FDSOI Technology for Computer Vision Applications.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

NCFET-Aware Voltage Scaling.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Performance, Power and Cooling Trade-Offs with NCFET-based Many-Cores.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

BSIM-BULK: Accurate Compact Model for Analog and RF Circuit Design.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance.
IEEE Access, 2018

Non-Linear RF Modeling of GaN HEMTs with Industry Standard ASM GaN Model (Invited).
Proceedings of the 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2018

2017
Modeling of Body-Bias Dependence of Overlap Capacitances in Bulk MOSFETs.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

2016
Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG.
Microelectron. J., 2016

Unified Model for Sub-Bandgap and Conventional Impact Ionization in RF SOI MOSFETs with Improved Simulator Convergence.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Analysis of Quantum Capacitance Effect in Ultra-Thin-Body III-V Transistor.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
Modeling STI Edge Parasitic Current for Accurate Circuit Simulations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

BSIM-CMG: Standard FinFET compact model for advanced circuit design.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
BSIM6 - Benchmarking the Next-Generation MOSFET Model for RF Applications.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

2013
BSIM - SPICE Models Enable FinFET and UTB IC Designs.
IEEE Access, 2013

BSIM compact MOSFET models for SPICE simulation.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

2012
BSIM - Industry standard compact MOSFET models.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Evaluation of the BSIM6 compact MOSFET model's scalability in 40nm CMOS technology.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2010
RF SOI Switch FET Design and Modeling Tradeoffs for GSM Applications.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2008
Compact Modeling of Suspended Gate FET.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007
A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET Modeling.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Suspended-gate FET as a sleep transistor for ultra-low stand-by power applications.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

2006
A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006


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