Bart Durinck

According to our database1, Bart Durinck authored at least 5 papers between 2004 and 2008.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2008
Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2006
A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies.
Proceedings of the 43rd Design Automation Conference, 2006

2005
A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck.
Proceedings of the 2005 Design, 2005

2004
Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications.
Proceedings of the Computer Systems: Architectures, 2004


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