Francky Catthoor

According to our database1, Francky Catthoor authored at least 589 papers between 1988 and 2018.

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2018
Runtime Slack Creation for Processor Performance Variability using System Scenarios.
ACM Trans. Design Autom. Electr. Syst., 2018

Energy-Efficient Mapping of LTE-A PHY Signal Processing Tasks on Microservers.
TGCN, 2018

Algorithm/Architecture Co-optimisation Technique for Automatic Data Reduction of Wireless Read-Out in High-Density Electrode Arrays.
ACM Trans. Embedded Comput. Syst., 2018

Runtime Precomputation of Data-Dependent Parameters in Embedded Systems.
ACM Trans. Embedded Comput. Syst., 2018

Unsupervised heart-rate estimation in wearables with Liquid states and a probabilistic readout.
Neural Networks, 2018

A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability.
Microelectronics Reliability, 2018

Impact and mitigation of SRAM read path aging.
Microelectronics Reliability, 2018

Techniques for dynamic hardware management of streaming media applications using a framework for system scenarios.
Microprocessors and Microsystems - Embedded Hardware Design, 2018

Device aging: A reliability and security concern.
Proceedings of the 23rd IEEE European Test Symposium, 2018

Towards high-performance polarity-controllable FETs with 2D materials.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Degradation analysis of high performance 14nm FinFET SRAM.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Mapping of local and global synapses on spiking neuromorphic hardware.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Impact of Address Generation on Multimedia Embedded VLIW Processors.
Proceedings of the Computer Information Systems and Industrial Management, 2018

2017
Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads.
IEEE Trans. VLSI Syst., 2017

Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier.
IEEE Trans. VLSI Syst., 2017

A MATLAB Vectorizing Compiler Targeting Application-Specific Instruction Set Processors.
ACM Trans. Design Autom. Electr. Syst., 2017

Parameterized Dataflow Scenarios.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Worst-case performance analysis of SDF-based parameterized dataflow.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

Will Chips of the Future Learn How to Feel Pain and Cure Themselves?
IEEE Design & Test, 2017

Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital Systems.
ACM Comput. Surv., 2017

Unsupervised Heart-rate Estimation in Wearables With Liquid States and A Probabilistic Readout.
CoRR, 2017

Failure probability of a FinFET-based SRAM cell utilizing the most probable failure point.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Energy Efficient Adaptive Approach for Dependable Performance in the presence of Timing Interference.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017


Wave pipelining for majority-based beyond-CMOS technologies.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Mitigation of sense amplifier degradation using input switching.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Array Size Computation under Uniform Overlapping and Irregular Accesses.
ACM Trans. Design Autom. Electr. Syst., 2016

Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD Architectures.
ACM Trans. Embedded Comput. Syst., 2016

Near-Static Shading Exploration for Smart Photovoltaic Module Topologies Based on Snake-like Configurations.
ACM Trans. Embedded Comput. Syst., 2016

Data Flow Transformation for Energy-Efficient Implementation of Givens Rotation-Based QRD.
ACM Trans. Embedded Comput. Syst., 2016

Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Accuracy of Quasi-Monte Carlo technique in failure probability estimations.
Proceedings of the International Conference on IC Design and Technology, 2016

Using an adaptive and time predictable runtime system for power-aware HPC-oriented applications.
Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

Capturing True Workload Dependency of BTI-induced Degradation in CPU Components.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Read path degradation analysis in SRAM.
Proceedings of the 21th IEEE European Test Symposium, 2016

Dynamic Hardware Management of the H264/AVC Encoder Control Structure Using a Framework for System Scenarios.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Comparative BTI analysis for various sense amplifier designs.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Approximating Standard Cell Delay Distributions by Reformulating the Most Probable Failure Point.
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016

Matlab to C compilation targeting Application Specific Instruction Set Processors.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Memories for NTC.
Proceedings of the Near Threshold Computing, Technology, Methods and Applications., 2016

2015
Demonstrating HW-SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane.
IEEE Trans. VLSI Syst., 2015

A Scalable MIMO Detector Processor With Near-ASIC Energy Efficiency.
IEEE Trans. VLSI Syst., 2015

Array Interleaving - An Energy-Efficient Data Layout Transformation.
ACM Trans. Design Autom. Electr. Syst., 2015

Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems.
ACM Trans. Embedded Comput. Syst., 2015

Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations.
ACM Comput. Surv., 2015

Tackling Performance Variability Due to RAS Mechanisms with PID-Controlled DVFS.
Computer Architecture Letters, 2015

Integral impact of BTI and voltage temperature variation on SRAM sense amplifier.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

HARPA: Solutions for dependable performance under physically induced performance variability.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Characterization of time-dependent variability using 32k transistor arrays in an advanced HK/MG technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

BTI analysis of SRAM write driver.
Proceedings of the 10th International Design & Test Symposium, 2015

Impact of time-dependent variability on the yield and performance of 6T SRAM cells in an advanced HK/MG technology.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

The defect-centric perspective of device and circuit reliability - From individual defects to circuits.
Proceedings of the 45th European Solid State Device Research Conference, 2015

Parametrized dataflow scenarios.
Proceedings of the 2015 International Conference on Embedded Software, 2015

System scenario framework evaluation on EFM32 using the H264/AVC encoder control structure.
Proceedings of the European Conference on Circuit Theory and Design, 2015

Comparative analysis of RD and Atomistic trap-based BTI models on SRAM Sense Amplifier.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Worst-Case Throughput Analysis of SDF-Based Parametrized Dataflow.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

System level exploration of a STT-MRAM based level 1 data-cache.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Memristor based computation-in-memory architecture for data-intensive applications.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Worst-case latency analysis of SDF-based parametrized dataflow MoCs.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015

Energy efficient FFT implementation through stage skipping and merging.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

Characterization and simulation methodology for time-dependent variability in advanced technologies.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
Configuration Mapping Algorithms to Reduce Energy and Time Reconfiguration Overheads in Reconfigurable Systems.
IEEE Trans. VLSI Syst., 2014

OCEAN: An Optimized HW/SW Reliability Mitigation Approach for Scratchpad Memories in Real-Time SoCs.
ACM Trans. Embedded Comput. Syst., 2014

A scalable and near-optimal representation of access schemes for memory management.
TACO, 2014

Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path.
IEICE Transactions, 2014

System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform.
Embedded Systems Letters, 2014

Worst-case Throughput Analysis for Parametric Rate and Parametric Actor Execution Time Scenario-Aware Dataflow Graphs.
Proceedings of the Proceedings 1st International Workshop on Synthesis of Continuous Parameters, 2014

Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

Systematic Exploration of Power-Aware Scenarios for IEEE 802.11ac WLAN Systems.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

NBTI Aging on 32-Bit Adders in the Downscaling Planar FET Technology Nodes.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Energy efficient data flow transformation for Givens Rotation based QR Decomposition.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Energy efficient MIMO processing: A case study of opportunistic run-time approximations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Feasibility exploration of NVM based I-cache through MSHR enhancements.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Bias Temperature Instability analysis of FinFET based SRAM cells.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Resolving the memory bottleneck for single supply near-threshold computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Adaptive Mapping and Parameter Selection Scheme to Improve Automatic Code Generation for GPUs.
Proceedings of the 12th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2014

2013
Design Space Exploration of Distributed Loop Buffer Architectures with Incompatible Loop-Nest Organisations in Embedded Systems.
Signal Processing Systems, 2013

Survey of Low-Energy Techniques for Instruction Memory Organisations in Embedded Systems.
Signal Processing Systems, 2013

Near-optimal and scalable intrasignal in-place optimization for non-overlapping and irregular access schemes.
ACM Trans. Design Autom. Electr. Syst., 2013

System-level memory management based on statistical variability compensation for frame-based applications.
ACM Trans. Embedded Comput. Syst., 2013

Polyhedral parallel code generation for CUDA.
TACO, 2013

Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints.
TACO, 2013

System scenarios-based architecture level exploration of SDR application using a network-on-chip simulation framework.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

Impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based BTI model.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

Enabling Efficient System Configurations for Dynamic Wireless Applications Using System Scenarios.
IJWIN, 2013

Design exploration of a NVM based hybrid instruction memory organization for embedded platforms.
Design Autom. for Emb. Sys., 2013

Exploration of energy efficient memory organisations for dynamic multimedia applications using system scenarios.
Design Autom. for Emb. Sys., 2013

A systematic approach to classify design-time global scheduling techniques.
ACM Comput. Surv., 2013

Energy impact in the design space exploration of loop buffer schemes in embedded systems.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Cracking the complexity of fixed-point refinement in complex wireless systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Impact of partial resistive defects and Bias Temperature Instability on SRAM decoder reliablity.
Proceedings of the 8th International Design and Test Symposium, 2013

Data memory optimization in LTE downlink.
Proceedings of the IEEE International Conference on Acoustics, 2013

Bias temperature instability analysis in SRAM decoder.
Proceedings of the 18th IEEE European Test Symposium, 2013

Early exploration for platform architecture instantiation with multi-mode application partitioning.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Power Impact of Loop Buffer Schemes for Biomedical Wireless Sensor Nodes.
Sensors, 2012

Ultra Low-Energy SRAM Design for Smart Ubiquitous Sensors.
IEEE Micro, 2012

Memory and communication driven spatio-temporal scheduling on MPSoCs.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

A template-based methodology for efficient microprocessor and FPGA accelerator co-design.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Memory-aware system scenario approach energy impact.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

IMOSIM: Exploration tool for Instruction Memory Organisations based on accurate cycle-level energy modelling.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Impact of Duty Factor, Stress Stimuli, and Gate Drive Strength on Gate Delay Degradation with an Atomistic Trap-Based BTI Model.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Partitioning and Assignment Exploration for Multiple Modes of IEEE 802.11n Modem on Heterogeneous MPSoC Platforms.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Incorporating parameter variations in BTI impact on nano-scale logical gates analysis.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

BTI impact on logical gates in nano-scale CMOS technology.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A hybrid HW-SW approach for intermittent error mitigation in streaming-based embedded systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Sub-word Handling in Data-parallel Mapping.
Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012

2011
Energy Aware Signal Processing for Software Defined Radio Baseband Implementation.
Signal Processing Systems, 2011

Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors.
Signal Processing Systems, 2011

An Extension to Fuzzy Cognitive Maps for Classification and Prediction.
IEEE Trans. Fuzzy Systems, 2011

Fast multidimension multichoice knapsack heuristic for MP-SoC runtime management.
ACM Trans. Embedded Comput. Syst., 2011

Methodology for Energy-Flexibility Space Exploration and Mapping of Multimedia Applications to Single-Processor Platform Styles.
IEEE Trans. Circuits Syst. Video Techn., 2011

A 4.4 pJ/Access 80 MHz, 128 kbit Variability Resilient SRAM With Multi-Sized Sense Amplifier Redundancy.
J. Solid-State Circuits, 2011

A Lightweight Security Scheme for Wireless Body Area Networks: Design, Energy Evaluation and Proposed Microprocessor Design.
J. Medical Systems, 2011

A probabilistic fuzzy approach to modeling nonlinear systems.
Neurocomputing, 2011

Systematic Design Principles for Cost-Effective Hard Constraint Management in Dynamic Nonlinear Systems.
IJARAS, 2011

Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Enabling efficient system configurations for dynamic wireless baseband engines using system scenarios.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

High level analysis of trade-offs across different partitioning schemes for wireless applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

Automated architecture exploration for low energy reconfigurable AGU.
Proceedings of the International SoC Design Conference, 2011

On the Value of Prediction in Opportunistic Radio Systems.
Proceedings of IEEE International Conference on Communications, 2011

Scalable Block-Based Parallel Lattice Reduction Algorithm for an SDR Baseband Processor.
Proceedings of IEEE International Conference on Communications, 2011

8T SRAM with Mimicked Negative Bit-lines and Charge Limited Sequential sense amplifier for wireless sensor nodes.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

NBTI Monitoring and Design for Reliability in Nanoscale Circuits.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2010
Run-time Task Overlapping on Multiprocessor Platforms.
Signal Processing Systems, 2010

Statistical Performance Analysis and Estimation for Parallel Multimedia Processing.
Signal Processing Systems, 2010

A Distributed Multichannel MAC Protocol for Multihop Cognitive Radio Networks.
IEEE Trans. Vehicular Technology, 2010

Control for Power Gating of Wires.
IEEE Trans. VLSI Syst., 2010

Implementation of Fuzzy Cognitive Maps Based on Fuzzy Neural Network and Application in Prediction of Time Series.
IEEE Trans. Fuzzy Systems, 2010

Modeling and exploiting spatial locality trade-offs in wavelet-based applications under varying resource requirements.
ACM Trans. Embedded Comput. Syst., 2010

Future Software-Defined Radio Platforms and Mapping Flows.
IEEE Signal Process. Mag., 2010

Design of fuzzy cognitive maps using neural networks for predicting chaotic time series.
Neural Networks, 2010

Software metadata: Systematic characterization of the memory behaviour of dynamic applications.
Journal of Systems and Software, 2010

Reliability-Aware Proactive Energy Management in Hard Real-Time Systems: A Motivational Case Study.
IJARAS, 2010

Experience with Widening Based Equivalence Checking in Realistic Multimedia Systems.
J. Electronic Testing, 2010

Ultra low energy Domain Specific Instruction-set Processor for on-line surveillance.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

Energy Efficiency Using Loop Buffer based Instruction Memory Organizations.
Proceedings of the International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, 2010

PinComm: Characterizing Intra-application Communication for the Many-Core Era.
Proceedings of the 16th IEEE International Conference on Parallel and Distributed Systems, 2010

Exploration of cryptographic ASIP designs for wireless sensor nodes.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Fast performance evaluation of fixed-point systems with un-smooth operators.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Quantization mode opportunities in fixed-point system design.
Proceedings of the 18th European Signal Processing Conference, 2010

An RDL-configurable 3D memory tier to replace on-chip SRAM.
Proceedings of the Design, Automation and Test in Europe, 2010

Exploiting finite precision information to guide data-flow mapping.
Proceedings of the 47th Design Automation Conference, 2010

A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms.
Proceedings of the 47th Design Automation Conference, 2010

Statistical approach in a system level methodology to deal with process variation.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009
Energy-performance Exploration of a CGA-based SDR Processor.
Signal Processing Systems, 2009

Energy Aware Algorithm and Implementation of SDR Oriented HSDPA Chip Level Equalizer.
Signal Processing Systems, 2009

Exploiting Varying Resource Requirements in Wavelet-based Applications in Dynamic Execution Environments.
Signal Processing Systems, 2009

Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning.
IEEE Trans. VLSI Syst., 2009

Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures.
IEEE Trans. VLSI Syst., 2009

Generic Multiphase Software Pipelined Partial FFT on Instruction Level Parallel Architectures.
IEEE Trans. Signal Processing, 2009

Playing the trade-off game: Architecture exploration using Coffeee.
ACM Trans. Design Autom. Electr. Syst., 2009

Trade-offs in loop transformations.
ACM Trans. Design Autom. Electr. Syst., 2009

System-scenario-based design of dynamic embedded systems.
ACM Trans. Design Autom. Electr. Syst., 2009

Spatial locality exploitation for runtime reordering of JPEG2000 wavelet data layouts.
ACM Trans. Design Autom. Electr. Syst., 2009

Stream-Centric Stereo Matching and View Synthesis: A High-Speed Approach on GPUs.
IEEE Trans. Circuits Syst. Video Techn., 2009

Scheduling and Resource Allocation for SVC Streaming Over OFDM Downlink Systems.
IEEE Trans. Circuits Syst. Video Techn., 2009

Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures.
IEEE Trans. Computers, 2009

EMPIRE: Empirical power/area/timing models for register files.
Microprocessors and Microsystems - Embedded Hardware Design, 2009

Optimization methodology of dynamic data structures based on genetic algorithms for multimedia embedded systems.
Journal of Systems and Software, 2009

Direct memory access usage optimization in network applications for reduced memory latency and energy consumption.
J. Embedded Computing, 2009

Accumulative Interference Modeling for Distributed Cognitive Radio Networks.
JCM, 2009

Dealing with data dependent conditions to enable general global source code transformations.
IJES, 2009

Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors.
IEICE Transactions, 2009

Locality optimization in a compiler for wireless applications.
Design Autom. for Emb. Sys., 2009

Register file exploration for a multi-standard wireless forward error correction ASIP.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study.
Proceedings of the Embedded Computer Systems: Architectures, 2009

Novel energy-efficient scalable soft-output SSFE MIMO detector architectures.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware Platforms.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Parallelization exploration of wireless applications using MPA.
Proceedings of the Parallel Computing: From Multicores and GPU's to Petascale, 2009

A Spatial Learning Algorithm for IEEE 802.11 Networks.
Proceedings of IEEE International Conference on Communications, 2009

A System Level Algorithmic Approach toward Energy-Aware SDR Baseband Implementations.
Proceedings of IEEE International Conference on Communications, 2009

Real-time stereo matching: A cross-based local approach.
Proceedings of the IEEE International Conference on Acoustics, 2009

Experience with widening based equivalence checking in realistic multimedia systems.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

Compilation Technique for Loop Overhead Minimization.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Simulation framework for early phase exploration of SDR platforms: A case study of platform dimensioning.
Proceedings of the Design, Automation and Test in Europe, 2009

Finite precision processing in wireless applications.
Proceedings of the Design, Automation and Test in Europe, 2009

Algorithm-architecture co-design of soft-output ML MIMO detector for parallel application specific instruction set processors.
Proceedings of the Design, Automation and Test in Europe, 2009

System-level power/performance evaluation of 3D stacked DRAMs for mobile applications.
Proceedings of the Design, Automation and Test in Europe, 2009

SARA: StreAm register allocation.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

System-level process variability compensation on memory organizations: on the scalability of multi-mode memories.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Synthesis of Runtime Switchable Pareto Buffers Offering Full Range Fine Grained Energy/Delay Trade-Offs.
Signal Processing Systems, 2008

Address Generation Optimization for Embedded High-Performance Processors: A Survey.
Signal Processing Systems, 2008

Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications.
Signal Processing Systems, 2008

Storage Estimation and Design Space Exploration Methodologies for the Memory Management of Signal Processing Applications.
Signal Processing Systems, 2008

MEERA: Cross-Layer Methodology for Energy Efficient Resource Allocation in Wireless Networks.
IEEE Trans. Wireless Communications, 2008

Performance Analysis of Slotted Carrier Sense IEEE 802.15.4 Medium Access Layer.
IEEE Trans. Wireless Communications, 2008

Combining system scenarios and configurable memories to tolerate unpredictability.
ACM Trans. Design Autom. Electr. Syst., 2008

Efficiently scheduling runtime reconfigurations.
ACM Trans. Design Autom. Electr. Syst., 2008

Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip.
IEEE Trans. Computers, 2008

The formalism underlying EASYMAP.
Sci. Comput. Program., 2008

Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures.
Integration, 2008

Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling.
IEICE Transactions, 2008

Energy-Efficient Bandwidth Allocation for Multiuser Scalable Video Streaming over WLAN.
EURASIP J. Wireless Comm. and Networking, 2008

Performance Analysis of Slotted Carrier Sense IEEE 802.15.4 Acknowledged Uplink Transmissions.
Proceedings of the WCNC 2008, IEEE Wireless Communications & Networking Conference, March 31 2008, 2008

Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Application-driven adaptive fixed-point refinement for SDRs.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

A unified instruction set programmable architecture for multi-standard advanced forward error correction.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

An implementation friendly low complexity multiplierless LLR generator for soft MIMO sphere decoders.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Anisotropic local high-confidence voting for accurate stereo correspondence.
Proceedings of the Image Processing: Algorithms and Systems VI, 2008

Selective Spanning with Fast Enumeration: A Near Maximum-Likelihood MIMO Detector Designed for Parallel Programmable Baseband Architectures.
Proceedings of IEEE International Conference on Communications, 2008

Downlink OFDM Scheduling and Resource Allocation for Delay Constraint SVC Streaming.
Proceedings of IEEE International Conference on Communications, 2008

Spatial locality trade-offs of wavelet-based applications in dynamic execution environments.
Proceedings of the IEEE International Conference on Acoustics, 2008

Bridging the energy gap in size, weight and power constrained software defined radio: Agile baseband processing as a key enabler.
Proceedings of the IEEE International Conference on Acoustics, 2008

Coffee: COmpiler Framework for Energy-Aware Exploration.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008

A tool flow for predicting system level timing failures due to interconnect reliability degradation.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Throughput Modeling of Large-Scale 802.11 Networks.
Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November, 2008

Adaptive SSFE Near-ML MIMO Detector with Dynamic Search Range and 80-103Mbps Flexible Implementation.
Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November, 2008

How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Scenario-Based Fixed-point Data Format Refinement to Enable Energy-scalable Software Defined Radios.
Proceedings of the Design, Automation and Test in Europe, 2008

Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications.
Proceedings of the Design, Automation and Test in Europe, 2008

Optimizing Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures.
Proceedings of the Design, Automation and Test in Europe, 2008

How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach.
Proceedings of the 45th Design Automation Conference, 2008

Accumulative Interference Modeling for Cognitive Radios with Distributed Channel Access.
Proceedings of the 3rd International ICST Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2008

Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Operation shuffling over cycle boundaries for low energy L0 clustering.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007
MEERA: cross-layer methodology for energy efficient resource allocation in wireless networks.
IEEE Trans. Wireless Communications, 2007

Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture.
IEEE Trans. VLSI Syst., 2007

A practical dynamic single assignment transformation.
ACM Trans. Design Autom. Electr. Syst., 2007

Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors.
ACM Trans. Design Autom. Electr. Syst., 2007

Incremental hierarchical memory size estimation for steering of loop transformations.
ACM Trans. Design Autom. Electr. Syst., 2007

Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Optimizing data structures at the modeling level in embedded multimedia.
Journal of Systems Architecture, 2007

Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinement.
Journal of Systems Architecture, 2007

Energy-aware compilation and hardware design for VLIW embedded systems.
IJES, 2007

Design-time application mapping and platform exploration for MP-SoC customised run-time management.
IET Computers & Digital Techniques, 2007

Memory hierarchy for high-performance and energyaware reconfigurable systems.
IET Computers & Digital Techniques, 2007

SmartMIMO: An Energy-Aware Adaptive MIMO-OFDM Radio Link Control for Next-Generation Wireless Local Area Networks.
EURASIP J. Wireless Comm. and Networking, 2007

A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware
CoRR, 2007

Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives
CoRR, 2007

Functional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source Code
CoRR, 2007

A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck
CoRR, 2007

A Wavelet-FFT Based Efficient Sparse OFDMA Demodulator and Its Implementation on VLIW Architecture.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Systematic Optimization of Programmable QRD Implementation for Multiple Application Scenarios.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Systematic intermediate sequence removal for reduced memory accesses.
Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems, 2007

Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation.
Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems, 2007

Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Semi Custom Design: A Case Study on SIMD Shufflers.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

High-Speed Stream-Centric Dense Stereo and View Synthesis on Graphics Hardware.
Proceedings of the IEEE 9th Workshop on Multimedia Signal Processing, 2007

Application - specific NoC platform design based on System Level Optimization.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Real-Time Stereo Correspondence using a Truncated Separable Laplacian Kernel Approximation on Graphics Hardware.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

Fast Variable Center-Biased Windowing for High-Speed Stereo on Programmable Graphics Hardware.
Proceedings of the International Conference on Image Processing, 2007

Fast Reliable Multi-Scale Motion Region Detection in Video Processing.
Proceedings of the IEEE International Conference on Acoustics, 2007

Efficient QRD for SRI-RLS Based Equalization on Programmable Architecture.
Proceedings of the IEEE International Conference on Acoustics, 2007

Energy-Efficient Bandwidth Allocation for Multi-User Video Streaming Over Wlan.
Proceedings of the IEEE International Conference on Acoustics, 2007

The Quality-Energy Scalable OFDMA Modulation for Low Power Transmitter and VLIW Processor Based Implementation.
Proceedings of the Global Communications Conference, 2007

Network-adaptive and energy-efficient multi-user video communication over QOS enabled WLAN.
Proceedings of the 15th European Signal Processing Conference, 2007

Run-time Task Overlapping on Multiprocessor Platforms.
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007

Adaptive mapping to resource availability for dynamic wavelet-based applications.
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007

Reducing the reconfiguration overhead: a survey of techniques.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

Very wide register: an asymmetric register file organization for low power embedded processors.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Middleware design optimization of wireless protocols based on the exploitation of dynamic input patterns.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Fast memory footprint estimation based on maximal dependency vector calculation.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A Distributed Multichannel MAC Protocol for Cognitive Radio Networks with Primary User Recognition.
Proceedings of the 2nd International ICST Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2007

Locality optimization in wireless applications.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

At Tape-out: Can System Yield in Terms of Timing/Energy Specifications Be Predicted?
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Topology exploration for energy efficient intra-tile communication.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors.
Proceedings of the Architecture of Computing Systems, 2007

2006
Platform independent optimisation of multi-resolution 3D content to enable universal media access.
The Visual Computer, 2006

A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck.
IEEE Trans. VLSI Syst., 2006

Systematic dynamic memory management design methodology for reduced memory footprint.
ACM Trans. Design Autom. Electr. Syst., 2006

Reuse analysis of indirectly indexed arrays.
ACM Trans. Design Autom. Electr. Syst., 2006

Eliminating CPU overhead for on-the-fly content adaptation with MPEG-4 wavelet subdivision surfaces.
IEEE Trans. Consumer Electronics, 2006

Cross-layer power management in wireless networks and consequences on system-level architecture.
Signal Processing, 2006

Systematic Preprocessing of Data Dependent Constructs for Embedded Systems.
J. Low Power Electronics, 2006

Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems.
Integration, 2006

Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance.
Computer Communications, 2006

Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System Design.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Energy-Aware MPEG-4 Single Profile in HW-SW Multi-Platform Implementation.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Exploit Multiple-Domain Sparseness for HSDPA Chip Level Equalization in SDR: Algorithm and DSP Implementation.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Software-Controlled Scratchpad Mapping Strategies for Wavelet-Based Applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

SmartMIMO: Energy-Aware Adaptive MIMO-OFDM Radio Link Control for Wireless Local Area Networks.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Instruction Transfer And Storage Exploration for Low Energy VLIWs.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Pareto-Based Application Specification for MP-SoC Customized Run-Time Management.
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Statistical Performance Analysis and Estimation of Coarse Grain Parallel Multimedia Processing System.
Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2006), 2006

Streaming-Mode MB-Based Integral Image Techniques for Fast Multi-view Video Illumination Compensation.
Proceedings of the Advances in Multimedia Information Processing, 2006

Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Compiler-Driven Leakage Energy Reduction in Banked Register Files.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Derivation of Packing Instructions for Exploiting Sub-Word Parallelism.
Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

On the Combined Impact of Soft and Medium Gate Oxide Breakdown and Process Variability on the Parametric Figures of SRAM components.
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006

System-level process variability compensation on memory organizations of dynamic applications: a case study.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Systematic design flow for dynamic data management in visual texture decoder of MPEG-4.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Template-Based Semi-Automatic Profiling of Multimedia Applications.
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006

Performance Analysis of Slotted Carrier Sense IEEE 802.15.4 Medium Access Layer.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

Quality-Energy Scalable Chip Level Equalization for HSDPA.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

Energy-efficient dynamic memory allocators at the middleware level of embedded systems.
Proceedings of the 6th ACM & IEEE International conference on Embedded software, 2006

Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Scalable performance-energy trade-off exploration of embedded real-time systems on multiprocessor platforms.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Energy-scalable OFDM transmitter design and control.
Proceedings of the 43rd Design Automation Conference, 2006

Distributed cognitive coexistence of 802.15.4 with 802.11.
Proceedings of the 1st International ICST Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2006

Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applications.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Physical design implementation of segmented buses to reduce communication energy.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Analysis of scratch-pad and data-cache performance using statistical methods.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Dynamic Voltage Scaling for Power Efficient MPEG4-SP Implementation.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

Loop Transformation Methodologies for Array-Oriented Memory Management.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications.
VLSI Signal Processing, 2005

Energy Efficient Memory Architecture for High Speed Decoding of Block Turbo-Codes with the Fang-Buda Algorithm.
VLSI Signal Processing, 2005

Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs.
IEEE Trans. VLSI Syst., 2005

Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications.
IEEE Trans. Computers, 2005

Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors.
IEEE Trans. Computers, 2005

Energy-aware Dynamic Task Scheduling Applied to a Real-time Multimedia Application on an Xscale Board.
J. Low Power Electronics, 2005

Optimized memory requirements for wavelet-based scalable multimedia codecs.
J. Embedded Computing, 2005

Instruction buffering exploration for low energy embedded processors.
J. Embedded Computing, 2005

Optimizing Transmission and Shutdown for Energy-Efficient Real-time Packet Scheduling in Clustered Ad Hoc Networks.
EURASIP J. Wireless Comm. and Networking, 2005

A Reconfiguration Manager for Dynamically Reconfigurable Hardware.
IEEE Design & Test of Computers, 2005

Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications.
Proceedings of the Wired/Wireless Internet Communications, Third International Conference, 2005

Pareto based optimization of multi-resolution geometry for real time rendering.
Proceedings of the Proceeding of the Tenth International Conference on 3D Web Technology, 2005

Global Memory Optimisation for Embedded Systems Allowed by Code Duplication.
Proceedings of the 9th International Workshop on Software and Compilers for Embedded Systems, Dallas, Texas, USA, September 29, 2005

Moving Up to the Modeling Level for the Transformation of Data Structures in Embedded Multimedia Applications.
Proceedings of the Embedded Computer Systems: Architectures, 2005

Energy Characterization of Garbage Collectors for Dynamic Applications on Embedded Systems.
Proceedings of the Integrated Circuit and System Design, 2005

Systematic Preprocessing of Data Dependent Constructs for Embedded Systems.
Proceedings of the Integrated Circuit and System Design, 2005

Improving the Memory Bandwidth Utilization Using Loop Transformations.
Proceedings of the Integrated Circuit and System Design, 2005

Performance Evaluation of Barrier Techniques for Distributed Tracing Garbage Collectors.
Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005

Pack Transposition: Enhancing Superword Level Parallelism Exploitation.
Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005

A novel approach for network on chip emulation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Object-Distribution Analysis for Program Decomposition and Re-Clustering.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Optimal fixed and scalable energy management for wireless networks.
Proceedings of the INFOCOM 2005. 24th Annual Joint Conference of the IEEE Computer and Communications Societies, 2005

Object-Distribution Analysis: Technique for Parallel Loop Distribution of Object-Oriented Programs.
Proceedings of the 34th International Conference on Parallel Processing Workshops (ICPP 2005 Workshops), 2005

Delay improvement of IEEE 802.11 distributed coordination function using size-based scheduling.
Proceedings of IEEE International Conference on Communications, 2005

Optimizing transmission and shutdown for energy-efficient packet scheduling in sensor networks.
Proceedings of the Wireless Sensor Networks, Second European Workshop, 2005

Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

Data-Access Optimization of Embedded Systems Through Selective Inlining Transformation.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

Combining Data and Instruction Memory Energy Optimizations for Embedded Applications.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules.
Proceedings of the 2005 Design, 2005

Functional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source Code.
Proceedings of the 2005 Design, 2005

A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware.
Proceedings of the 2005 Design, 2005

A Complete Network-On-Chip Emulation Framework.
Proceedings of the 2005 Design, 2005

A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck.
Proceedings of the 2005 Design, 2005

Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives.
Proceedings of the 2005 Design, 2005

Compiler-Based Approach for Exploiting Scratch-Pad in Presence of Irregular Array Access.
Proceedings of the 2005 Design, 2005

From myth to methodology: cross-layer design for energy-efficient wireless communication.
Proceedings of the 42nd Design Automation Conference, 2005

Improving superword level parallelism support in modern compilers.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Experiences with Enumeration of Integer Projections of Parametric Polytopes.
Proceedings of the Compiler Construction, 14th International Conference, 2005

Verification of Source Code Transformations by Program Equivalence Checking.
Proceedings of the Compiler Construction, 14th International Conference, 2005

Hierarchical task scheduler for interleaving subtasks on heterogeneous multiprocessor platforms.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

Transformation to Dynamic Single Assignment Using a Simple Data Flow Analysis.
Proceedings of the Programming Languages and Systems, Third Asian Symposium, 2005

2004
Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors.
VLSI Signal Processing, 2004

Memory-access-aware data structure transformations for embedded software with dynamic data accesses.
IEEE Trans. VLSI Syst., 2004

Storage requirement estimation for optimized design of data intensive applications.
ACM Trans. Design Autom. Electr. Syst., 2004

A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs.
Microprocessors and Microsystems, 2004

Formally Specifying Dynamic Data Structures for Embedded Software Design: an Initial Approach.
Electr. Notes Theor. Comput. Sci., 2004

Integrated Task Scheduling and Data Assignment for SDRAMs in Dynamic Applications.
IEEE Design & Test of Computers, 2004

A Framework for Data Partitioning for C++ Data-Intensive Applications.
Design Autom. for Emb. Sys., 2004

Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology.
Proceedings of the Wired/Wireless Internet Communications, Second International Conference, 2004

Dynamic Mapping and Ordering Tasks of Embedded Real-Time Systems on Multiprocessor Platforms.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004

An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004

Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications.
Proceedings of the Computer Systems: Architectures, 2004

L0 buffer energy optimization through scheduling and exploration.
Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004

Design Style Case Study for Embedded Multi Media Compute Nodes.
Proceedings of the 25th IEEE Real-Time Systems Symposium (RTSS 2004), 2004

L0 Cluster Synthesis and Operation Shuffling.
Proceedings of the Integrated Circuit and System Design, 2004

Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems.
Proceedings of the Integrated Circuit and System Design, 2004

Fast prototyping and refinement of complex dynamic data types in multimedia applications for consumer embedded devices.
Proceedings of the 2004 IEEE International Conference on Multimedia and Expo, 2004

High-Level Data-Access Analysis for Characterisation of (Sub)task-Level Parallelism in Java.
Proceedings of the 9th International Workshop on High-Level Programming Models and Supportive Environments (HIPS 2004), 2004

Design-Time Data-Access Analysis for Parallel Java Programs with Shared-Memory Communication Model.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

Data assignment and access scheduling exploration for multi-layer memory architectures.
Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004

Low energy data and concurrency management of highly dynamic real-time multi-media systems.
Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004

Reducing memory accesses with a system-level design methodology in customized dynamic memory management.
Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004

Time-Energy Design Space Exploration for Multi-Layer Memory Architectures.
Proceedings of the 2004 Design, 2004

A Power Optimized Display Memory Organization for Handheld User Terminal.
Proceedings of the 2004 Design, 2004

How Can System-Level Design Solve the Interconnect Technology Scaling Problem?
Proceedings of the 2004 Design, 2004

Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications.
Proceedings of the 2004 Design, 2004

An integrated hardware/software approach for run-time scratchpad management.
Proceedings of the 41th Design Automation Conference, 2004

Optimizing the memory bandwidth with loop fusion.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Overcoming the "Memory Wall" by improved system design exploration and a link to process technology options.
Proceedings of the First Conference on Computing Frontiers, 2004

A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Instruction buffering exploration for low energy VLIWs with instruction clusters.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Optimizing the Memory Bandwidth with Loop Morphing.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

Garbage Collector Refinement for New Dynamic Multimedia Applications on Embedded Systems.
Proceedings of the 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 2004

2003
Guest Editorial: Special Issue on Signal Processing Systems: Part I.
VLSI Signal Processing, 2003

Guest Editorial: Special Issue on Signal Processing Systems: Part II.
VLSI Signal Processing, 2003

Memory Power Reduction for High-Speed Implementation of Turbo Codes.
VLSI Signal Processing, 2003

Power-efficient flexible processor architecture for embedded applications.
IEEE Trans. VLSI Syst., 2003

Search space definition and exploration for nonuniform data reuse opportunities in data-dominant applications.
ACM Trans. Design Autom. Electr. Syst., 2003

Special issue on power-aware embedded computing.
ACM Trans. Embedded Comput. Syst., 2003

A scalable MPEG-4 wavelet-based visual texture compression system with optimized memory organization.
IEEE Trans. Circuits Syst. Video Techn., 2003

Data dependency size estimation for use in memory optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

An Automatic Verification Technique for Loop and Data Reuse Transformations based on Geometric Modeling of Programs.
J. UCS, 2003

Efficient System-Level Functional Verification Methodology for Multimedia Applications.
IEEE Design & Test of Computers, 2003

Systematic Application of Data Transfer and Storage Optimizing Code Transformations for Power Consumption and Execution Time Reduction in ACROPOLIS: A Pre-Compiler for Multimedia Applications.
Design Autom. for Emb. Sys., 2003

Global interconnect trade-off for technology over memory modules to application level: case study.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java.
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003

Control Flow Analysis for Recursion Removal.
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003

Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level.
Proceedings of the Integrated Circuit and System Design, 2003

Memory Compaction and Power Optimization for Wavelet-Based Coders.
Proceedings of the Integrated Circuit and System Design, 2003

Instruction Buffering Exploration for Low Energy Embedded Processors.
Proceedings of the Integrated Circuit and System Design, 2003

Advanced copy propagation for arrays.
Proceedings of the 2003 Conference on Languages, 2003

Estimating influence of data layout optimizations on SDRAM energy consumption.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Power aware data type refinement on the HIPERLAN/2.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

Automatic functional verification of memory oriented global source code transformations.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

Run-Time Scheduling for Multimedia Applications on Dynamically Reconfigurable Systems.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003

Causality Constraints for Processor Architectures with Sub-Word Parallelism.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms.
Proceedings of the 2003 Design, 2003

Layer Assignment echniques for Low Energy in Multi-Layered Memory Organisations.
Proceedings of the 2003 Design, 2003

Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor.
Proceedings of the 2003 Design, 2003

Pareto-optimization-based run-time task scheduling for embedded systems.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Multi-dimentsional Incremetal Loops Fusion for Data Locality.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002
Dynamic memory management methodology applied to embedded telecom network systems.
IEEE Trans. VLSI Syst., 2002

A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors.
IEEE Trans. VLSI Syst., 2002

System-level exploration of association table implementations in telecom network applications.
ACM Trans. Embedded Comput. Syst., 2002

Matador: An Exploration Environment for System-Design.
Journal of Circuits, Systems, and Computers, 2002

Geometric Model Checking: An Automatic Verification Technique for Loop and Data Reuse Transformations.
Electr. Notes Theor. Comput. Sci., 2002

Incorporating energy efficient data structures into modular software implementations for internet-based embedded systems.
Workshop on Software and Performance, 2002

Storage Size Reduction by In-place Mapping of Arrays.
Proceedings of the Verification, 2002

Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Interconnect exploration for future wire dominated technologies.
Proceedings of the Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), 2002

A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Systematic Design of Programs with Sub-Word Parallelism.
Proceedings of the 2002 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2002), 2002

Multi-ovjective abstract data type refinement for mapping tables in telecom network applications.
Proceedings of The Workshop on Memory Systems Performance (MSP 2002), 2002

Managing Dynamic Concurrent Tasks in Embedded Real-Time Multimedia Systems.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Analyzing energy friendly steady state phases of dynamic application execution in terms of sparse data structures.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

A class of power efficient VLSI architectures for high speed turbo-decoding.
Proceedings of the Global Telecommunications Conference, 2002

Systematic Power-Performance Trade-Off in MPEG-4 by Means of Selective Function Inlining Steered by Address Optimization Opportunities.
Proceedings of the 2002 Design, 2002

Data Reuse Exploration Techniques for Loop-Dominated Application.
Proceedings of the 2002 Design, 2002

System-level performance optimization of the data queueing memory management in high-speed network processors.
Proceedings of the 39th Design Automation Conference, 2002

Data Access and Storage Management for Embedded Programmable Processors.
Kluwer, ISBN: 978-0-7923-7689-7, 2002

2001
Power and Speed-Efficient Code Transformation of Video Compression Algorithms for RISC Processors.
VLSI Signal Processing, 2001

A Systematic Approach to Reduce the System Bus Load and Power in Multimedia Algorithms.
VLSI Design, 2001

Memory optimization of MAP turbo decoder algorithms.
IEEE Trans. VLSI Syst., 2001

Data and memory optimization techniques for embedded systems.
ACM Trans. Design Autom. Electr. Syst., 2001

System-level data-format exploration for dynamically allocated datastructures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Energy-Aware Runtime Scheduling for Embedded-Multiprocessor SOCs.
IEEE Design & Test of Computers, 2001

Guest Editors' Intoduction: The New World of Large Embedded Memories.
IEEE Design & Test of Computers, 2001

Data Memory Organization and Optimizations in Application-Specific Systems.
IEEE Design & Test of Computers, 2001

Random-Access Data Storage Components in Customized Architectures.
IEEE Design & Test of Computers, 2001

Code Transformations for Data Transfer and Storage Exploration Preprocessing in Multimedia Processors.
IEEE Design & Test of Computers, 2001

Embedded Memories in System Design: Technology, Application, Design and Tools.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

A Systematic Approach for System Bus Load Reduction Applied to Medical Imaging.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

System-level interconnect architecture exploration for custom memory organizations.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Solving large scale assignment problems in high-level synthesis by approximative quadratic programming.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Topic 15+20: Multimedia and Embedded Systems.
Proceedings of the Euro-Par 2001: Parallel Processing, 2001

Task concurrency management methodology summary.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Cache conscious data layout organization for embedded multimedia applications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Detection of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data Intensive Applications.
Proceedings of the 38th Design Automation Conference, 2001

2000
A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints.
VLSI Signal Processing, 2000

Formalized three-layer system-level model and reuse methodology for embedded data-dominated applications.
IEEE Trans. VLSI Syst., 2000

Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel.
Parallel Algorithms Appl., 2000

The Local Wavelet Transform: a memory-efficient, high-speed architecture optimized to a Region-Oriented Zero-Tree coder.
Integrated Computer-Aided Engineering, 2000

Transformations of a 3D Image Reconstruction Algorithm for Data Transfer and Storage Optimisation.
Design Autom. for Emb. Sys., 2000

Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

A loop transformation approach for combined parallelization and data transfer and storage optimization.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform.
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000

Flexible hardware acceleration for multimedia oriented microprocessors.
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

Low Power Storage Cycle Budget Distribution Tool Support for Hierarchical Graphs.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Systematic Data Reuse Exploration Methodology for Irregular Access Patterns.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Systematic cycle budget versus system power trade-off: a new perspective on system exploration of real-time data-dominated applications.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Advanced Data Layout Optimization for Multimedia Applications.
Proceedings of the Parallel and Distributed Processing, 2000

Task Concurrency Management Experiment for Power-Efficient Speed-up of Embedded MPEG4 IM1 Player.
Proceedings of the 2000 International Workshop on Parallel Processing, 2000

Automated Data Dependency Size Estimation with a Partially Fixed Execution Ordering.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Multi-dimensional Selection Techniques for Minimizing Memory Bandwidth in High-Throughput Embedded Systems.
Proceedings of the High Performance Computing, 2000

Formalized Three-Layer System-Level Reuse Model and Methodology for Embedded Data-Dominated Applications.
Proceedings of the 2000 Design, 2000

Analysis of High-Level Address Code Transformations for Programmable Processors.
Proceedings of the 2000 Design, 2000

How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level?
Proceedings of the 2000 Design, 2000

Interactive co-design of high throughput embedded multimedia.
Proceedings of the 37th Conference on Design Automation, 2000

System-level data format exploration for dynamically allocated data structures.
Proceedings of the 37th Conference on Design Automation, 2000

Extended design reuse trade-offs in hardware-software architecture mapping.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

Storage requirement estimation for data intensive applications with partially fixed execution ordering.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

Dynamic scheduling of concurrent tasks with cost performance trade-off.
Proceedings of the 2000 International Conference on Compilers, 2000

A preprocessing step for global loop transformations for data transfer optimization.
Proceedings of the 2000 International Conference on Compilers, 2000

1999
Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management.
VLSI Signal Processing, 1999

System-Level Energy-Delay Exploration for Multimedia Applications on Embedded Cores with Hardware Cache.
VLSI Signal Processing, 1999

Energy-Delay Efficient Data Storage and Transfer Architectures and Methodologies: Current Solutions and Remaining Problems.
VLSI Signal Processing, 1999

Minimizing the required memory bandwidth in VLSI system realizations.
IEEE Trans. VLSI Syst., 1999

An efficient VLSI architecture for 2-D wavelet image coding with novel image scan.
IEEE Trans. VLSI Syst., 1999

Strategy for power-efficient design of parallel systems.
IEEE Trans. VLSI Syst., 1999

Low Power Memory Storage and Transfer Organization for the MPEG-4 Full Pel Motion Estimation on a Multimedia Processor.
IEEE Trans. Multimedia, 1999

Memory management for embedded network applications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Guest Editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Strategy for power efficient combined task and data parallelism exploration illustrated on a QSDPCM video codec.
Journal of Systems Architecture, 1999

Transformations of a 3D Image Reconstruction Algorithm for Data Transfer and Storage Optimization.
Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999

Platform Independent Data Transfer and Storage Exploration Illustrated on Parallel Cavity Detection Algorithm.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

Exploration and Synthesis of Dynamic Data Sets in Telecom Network Applications.
Proceedings of the 12th International Symposium on System Synthesis, 1999

Energy efficient data transfer and storage organization for a MAP turbo decoder module.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Interaction Between Data Parallel Compilation and Data Transfer and Storage Cost Minimization for Multimedia Applications.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

Exploiting Data Transfer Locality in Memory Mapping.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

Global Multimedia System Design Exploration Using Accurate Memory Organization Feedback.
Proceedings of the 36th Conference on Design Automation, 1999

1998
System-Level Power Optimization of Video Codecs on Embedded Cores: A Systematic Approach.
VLSI Signal Processing, 1998

System-Level Data-Flow Transformation Exploration and Power-Area Trade-offs Demonstrated on Video Codecs.
VLSI Signal Processing, 1998

Formalized methodology for data reuse: exploration for low-power hierarchical memory mappings.
IEEE Trans. VLSI Syst., 1998

High-level address optimization and synthesis techniques for data-transfer-intensive applications.
IEEE Trans. VLSI Syst., 1998

Program transformation strategies for memory size and power reduction of pseudoregular multimedia subsystems.
IEEE Trans. Circuits Syst. Video Techn., 1998

Low-power data transfer and storage exploration for H.263 video decoder system.
IEEE Journal on Selected Areas in Communications, 1998

Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation.
J. Electronic Testing, 1998

Power and speed-efficient code transformation of multimedia algorithms for RISC processors.
Proceedings of the Second IEEE Workshop on Multimedia Signal Processing, 1998

Proposal for Unified System Design Meta Flow in Task-Level and Instruction-Level Design Technology Research for Multi-Media Applications.
Proceedings of the 11th International Symposium on System Synthesis, 1998

Power exploration for dynamic data types through virtual memory management refinement.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Code Transformations for Low Power Caching in Embedded Multimedia Processors.
IPPS/SPDP, 1998

Code Transformations for Reduced Data Transfer and Storage in Low Power Realisations of MPEG-4 Full-Pel Motion Estimation.
Proceedings of the 1998 IEEE International Conference on Image Processing, 1998

Embedded memories in system design - from technology to systems architecture.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Hardware Cache Optimization for Parallel Multimedia Applications.
Proceedings of the Euro-Par '98 Parallel Processing, 1998

Energy-Delay Efficient Data Storage and Transfer Architectures: Circuit Technology versus Design Methodology Solutions.
Proceedings of the 1998 Design, 1998

Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Practical solutions for counting scalars and dependences in ATOMIUM-a memory management system for multidimensional signal processing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Memory Size Reduction Through Storage Order Optimization for Embedded Parallel Multimedia Applications.
Parallel Computing, 1997

Fast and Extensive System-Level Memory Exploration for ATM Applications.
Proceedings of the 10th International Symposium on System Synthesis, 1997

Formalized methodology for data reuse exploration in hierarchical memory mappings.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Low power design without compromise (panel).
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Architectural exploration and optimization for counter based hardware address generation.
Proceedings of the European Design and Test Conference, 1997

System level memory optimization for hardware-software co-design.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

Array Placement for Storage Size Reduction in Embedded Multimedia Systems.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996
Transforming set data types to power optimal data structures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Flow Graph Balancing for Minimizing the Required Memory Bandwidth.
Proceedings of the 9th International Symposium on System Synthesis, 1996

ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures.
Proceedings of the 9th International Symposium on System Synthesis, 1996

Power exploration for data dominated video applications.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Parallel Image/Video Processing and Computer Arithmetic.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

System-Level Memory Management for Weakly Parallel Image Processing.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

A Specification Invariant Technique for Regularity Improvement between Flow-Graph Clusters.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Formalisation of multi-precision arithmetic for high-level synthesis of DSP architectures.
VLSI Signal Processing, 1995

Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures.
VLSI Signal Processing, 1995

Background memory area estimation for multidimensional signal processing systems.
IEEE Trans. VLSI Syst., 1995

Quadratic zero-one programming-based synthesis of application-specific data paths.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

Mapping real-time motion estimation type algorithms to memory efficient, programmable multi-processor architectures.
Microprocessing and Microprogramming, 1995

Parallel programmable architectures and compilation for multi-dimensional processing.
Microprocessing and Microprogramming, 1995

Algorithms and parallel VLSI architectures.
Integration, 1995

Partial scan and symbolic test at the register-transfer level.
J. Electronic Testing, 1995

System level verification of video and image processing specifications.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Transforming set data types to power optimal data structures.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

Memory organization for video algorithms on programmable signal processors.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Background memory management for dynamic data structure intensive processing systems.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994
Cellular automata based deterministic self-test strategies for programmable data paths.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Transformation of Nested Loops with Modulo Indexing to Affine Recurrences.
Parallel Processing Letters, 1994

Design of a C-testable booth multiplier using a realistic fault model.
J. Electronic Testing, 1994

A specification invariant technique for operation cost minimisation in flow-graphs.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Is it Possible to achieve a Teraflop/s on a chip? From High Performance Algorithms to Architectures.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Design of heterogeneous ICs for mobile and personal communication systems.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Dataflow-driven memory allocation for multi-dimensional signal processing systems.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Control flow optimization for fast system simulation and storage minimization.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

An optimisation methodology for array mapping of affine recurrence equations in video and image processing.
Proceedings of the International Conference on Application Specific Array Processors, 1994

Loop transformation methodology for fixed-rate video, image and telecom processing applications.
Proceedings of the International Conference on Application Specific Array Processors, 1994

1993
Introduction.
VLSI Signal Processing, 1993

An application-specific architecture for the RBN-coder with efficient memory organization.
VLSI Signal Processing, 1993

Modeling multidimensional data and control flow.
IEEE Trans. VLSI Syst., 1993

Testability analysis in high level data path synthesis.
J. Electronic Testing, 1993

Test Algorithms for Double-Buffered Random Access and Pointer-Addressed Memories.
IEEE Design & Test of Computers, 1993

Partial Scan at the Register-Transfer Level.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Quadratic zero-one programming based synthesis of application specific data paths.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Exact evaluation of memory size for multi-dimensional signal processing systems.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992
Nonlinear transformations for high level regular array ASIC synthesis.
VLSI Signal Processing, 1992

Optimized synthesis of asynchronous control circuits from graph-theoretic specifications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

Combined hardware selection and pipelining in high-performance data-path design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

Optimized BIST Strategies for Programmable Data Paths Based on Cellular Automata.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Models for bit-true simulation and high-level synthesis of DSP applications.
Proceedings of the Second Great Lakes Symposium on VLSI, 1992

Time Constrained Allocation and Assignment Techniques for High Throughput Signal Processing.
Proceedings of the 29th Design Automation Conference, 1992

1991
In-place memory management of algebraic algorithms on application specific ICs.
VLSI Signal Processing, 1991

Synthesis of ASIC regular arrays for real-time image processing systems.
VLSI Signal Processing, 1991

Partitioning-Based Allocation of Dedicated Data-Paths in the Architectural Synthesis for High Throughput Applications.
VLSI, 1991

Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment.
Proceedings of the conference on European design automation, 1991

Affine transformations for multi-dimensional signal processing on ASIC regular arrays.
Proceedings of the conference on European design automation, 1991

Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP Applications.
Proceedings of the 28th Design Automation Conference, 1991

Signal analysis and signal transformations for ASIC regular array architecture synthesis.
Proceedings of the Algorithms and Parallel VLSI Architectures II, 1991

Array design methodologies for real-time signal processing in the CATHEDRAL-IV synthesis environment.
Proceedings of the Algorithms and Parallel VLSI Architectures II, 1991

1990
An integrated automatic design system for complex DSP algorithms.
VLSI Signal Processing, 1990

Efficient microcoded processor design for fixed rate DFT and FFT.
VLSI Signal Processing, 1990

Application-specific architectural methodologies for high-throughput digital signal and image processing.
IEEE Trans. Acoustics, Speech, and Signal Processing, 1990

Deriving ASIC architectures for the Hough transform.
Parallel Computing, 1990

Efficient VLSI Architectures for a High-Performance Digital Image Communication System.
IEEE Journal on Selected Areas in Communications, 1990

Cellular automata based self-test for programmable data paths.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Combined hardware selection and pipelining in high performance data-path design.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Optimized Synthesis of Asynchronous Control Circuits from Graph-Theoretic Specifications.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Open-ended system for high-level synthesis of flexible signal processors.
Proceedings of the European Design Automation Conference, 1990

1989
Definition and assignment of complex data-paths suited for high throughput applications.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988
Architectural strategies for an application-specific synchronous multiprocessor environment.
IEEE Trans. Acoustics, Speech, and Signal Processing, 1988

SAMURAI: A general and efficient simulated-annealing schedule with fully adaptive annealing parameters.
Integration, 1988


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