Barton Sano

According to our database1, Barton Sano authored at least 7 papers between 1990 and 2000.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2000
Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions.
IEEE Trans. Computers, 2000

Piranha: a scalable architecture based on single-chip multiprocessing.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

1998
Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications.
Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998

1996
Design and Analysis of Hardware for High-Performance Prolog.
J. Log. Program., 1996

1995
190-MHz CMOS 4-Kbyte Pipelined Caches.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1993
The 16-fold way: a microparallel taxonomy.
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

1990
Fast Prolog with an Extended General Purpose Architecture.
Proceedings of the 17th Annual International Symposium on Computer Architecture, 1990


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