Basma Hajri

According to our database, Basma Hajri authored at least 8 papers between 2017 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

A 2nm Clock-Edge Architecture for Processor Clock-Power Reduction.

Yimai Peng, Daniel Yingling, Basma Hajri, Robert Vachon, Fikre Tsigabu Gebreyohannes, Vincent Li, Ghanshyam Chhetri, Keith A. Bowman

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2025

A Novel Full Adder Design Using Hybrid Memristor Ratioed Logic.

Hussein Fadlallah, Rouwaida Kanj, Basma Hajri

Proceedings of the 26th International Symposium on Quality Electronic Design, 2025

2020

A Lightweight Reconfigurable RRAM-based PUF for Highly Secure Applications.

Basma Hajri, Mohammad M. Mansour, Ali Chehab, Hassen Aziza

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019

RRAM Device Models: A Comparative Analysis With Experimental Validation.

Basma Hajri, Hassen Aziza, Mohammad M. Mansour, Ali Chehab

IEEE Access, 2019

2018

A lightweight write-assist scheme for reduced RRAM variability and power.

Hassen Aziza, Basma Hajri, Mohammad M. Mansour, Ali Chehab, Annie Pérez

Microelectron. Reliab., 2018

Low power GDI ALU design with mixed logic adder functionality.

Jean Abou Rahal, Bassel Maamari, Basma Hajri, Rouwaida Kanj, Mohammad M. Mansour, Ali Chehab

Proceedings of the 2018 International Conference on IC Design & Technology, 2018

Memristor models optimization for large-scale 1T1R memory arrays.

Basma Hajri, Mohammad M. Mansour, Ali Chehab, Hassen Aziza

Proceedings of the 2018 International Conference on IC Design & Technology, 2018

2017

Oxide-based RRAM models for circuit designers: A comparative analysis.

Basma Hajri, Mohammad M. Mansour, Ali Chehab, Hassen Aziza

Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017