Rouwaida Kanj

According to our database1, Rouwaida Kanj authored at least 58 papers between 2002 and 2021.

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Bibliography

2021
Secure MIMO D2D communication based on a lightweight and robust PLS cipher scheme.
Wirel. Networks, 2021

Design Exploration of Sensing Techniques in 2T-2R Resistive Ternary CAMs.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

In-memory Multi-valued Associative Processor.
CoRR, 2021

Efficient Noise Mitigation Technique for Quantum Computing.
CoRR, 2021

Importance Splitting Sample Point Reuse for Efficient Memory Yield Estimation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Hybrid Importance Splitting Importance Sampling Methodology for Fast Yield Analysis of Memory Designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Threshold Switch Modeling for Analog CAM Design.
Proceedings of the 32nd International Conference on Microelectronics, 2020

2019
Verification at RTL Using Separation of Design Concerns.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Data Imbalance Handling Approaches for Accurate Statistical Modeling and Yield Analysis of Memory Designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

RRAM Endurance and Retention: Challenges, Opportunities and Implications on Reliable Design.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018
Sparse Regression Driven Mixture Importance Sampling for Memory Design.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Identity Based Key Distribution Framework for Link Layer Security of AMI Networks.
IEEE Trans. Smart Grid, 2018

Double error cellular automata-based error correction with skip-mode compact syndrome coding for resilient PUF design.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Low power GDI ALU design with mixed logic adder functionality.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018

2017
Regularized logistic regression for fast importance sampling based SRAM yield analysis.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Yield and energy tradeoffs of an NVLatch design using radial sampling.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

2016
A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Bayesian Model Fusion: Large-Scale Performance Modeling of Analog and Mixed-Signal Circuits by Reusing Early-Stage Data.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Automated FPGA implementations of BIP designs.
Proceedings of the 11th IEEE Symposium on Industrial Embedded Systems, 2016

Efficient analog circuit optimization using sparse regression and error margining.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2015
Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Corrections to "Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction".
IEEE Trans. Very Large Scale Integr. Syst., 2015

Separation of concerns for hardware components of embedded systems in BIP.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2014
PUF and ID-based key distribution security framework for advanced metering infrastructures.
Proceedings of the 2014 IEEE International Conference on Smart Grid Communications, 2014

Impact of FinFET technology for power gating in nano-scale design.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Statistical methodology for modeling non-IID memory fails events.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Robust bias temperature instability refresh design and methodology for memory cell recovery.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

2013
Hardware-corroborated Variability-Aware SRAM Methodology.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Low Cost Arduino/Android-Based Energy-Efficient Home Automation System with Smart Task Scheduling.
Proceedings of the Fifth International Conference on Computational Intelligence, 2013

2012
Isolated Preset Architecture for a 32nm SOI embedded DRAM macro.
Proceedings of the Symposium on VLSI Circuits, 2012

A novel sample reuse methodology for fast statistical simulations with applications to manufacturing variability.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

A thermal and process variation aware MTJ switching model and its applications in soft error analysis.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Yield estimation via multi-cones.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
The Impact of Statistical Leakage Models on Design Yield Estimation.
VLSI Design, 2011

A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Accelerated statistical simulation via on-demand Hermite spline interpolations.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Universal statistical cure for predicting memory loss.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane.
IEEE Des. Test Comput., 2010

FinFET SRAM Design.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Use of scalable Parametric Measurement Macro to improve semiconductor technology characterization and product test.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

2009
The impact of BEOL lithography effects on the SRAM cell performance and yield.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Statistical yield analysis of silicon-on-insulator embedded DRAM.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Yield estimation of SRAM circuits using "Virtual SRAM Fab".
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008
A Root-Finding Method for Assessing SRAM Stability.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

2007
Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Cross Layer Error Exploitation for Aggressive Voltage Scaling.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

A Disturb Decoupled Column Select 8T SRAM Cell.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
System-Level SRAM Yield Enhancement.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

SRAM Local Bit Line Access Failure Analyses.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events.
Proceedings of the 43rd Design Automation Conference, 2006

2004
Critical evaluation of SOI design guidelines.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Noise characterization of static CMOS gates.
Proceedings of the 41th Design Automation Conference, 2004

2002
A critical look at design guidelines for SOI logic gates.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002


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