Yimai Peng

Orcid: 0000-0001-9860-0175

According to our database1, Yimai Peng authored at least 10 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
14.3 A 3nm Adaptive Clock Duty-Cycle Controller for Mitigating Aging-Induced Clock Duty-Cycle Distortion.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A High-Voltage Generator and Multiplexer for Electrostatic Actuation in Programmable Matter.
IEEE J. Solid State Circuits, 2023

A 4.6nW Subthreshold Voltage Reference with 400× Current Variation Reduction and 64-Step 0.11% Output Voltage Programmability.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022
A 184nW, 121µg/√Hz Noise Floor Triaxial MEMS Accelerometer with Integrated CMOS Readout Circuit and Variation-Compensated High Voltage MEMS Biasing.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A 286nW, 103V High Voltage Generator and Multiplexer for Electrostatic Actuation in Programmable Matter.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Audio and Image Cross-Modal Intelligence via a 10TOPS/W 22nm SoC with Back-Propagation and Dynamic Power Gating.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2019
An Efficient Piezoelectric Energy Harvesting Interface Circuit Using a Sense-and-Set Rectifier.
IEEE J. Solid State Circuits, 2019

An Adiabatic Sense and Set Rectifier for Improved Maximum-Power-Point Tracking in Piezoelectric Harvesting with 541% Energy Extraction Gain.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A 0.04MM<sup>3</sup>16NW Wireless and Batteryless Sensor System with Integrated Cortex-M0+ Processor and Optical Communication for Cellular Temperature Measurement.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2017
A Side-Channel Attack Resistant AES with 500Mbps, 1.92pJ/Bit PVT Variation Tolerant True Random Number Generator.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017


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