Akram Ben Ahmed

Orcid: 0000-0002-1253-8620

According to our database1, Akram Ben Ahmed authored at least 40 papers between 2010 and 2023.

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Bibliography

2023
Power-Aware Neuromorphic Architecture With Partial Voltage Scaling 3-D Stacking Synaptic Memory.
IEEE Trans. Very Large Scale Integr. Syst., December, 2023

A Multi-FPGA Implementation of FM-Index Based Genomic Pattern Search.
IEICE Trans. Inf. Syst., November, 2023

METICULOUS: An FPGA-based Main Memory Emulator for System Software Studies.
CoRR, 2023

2022
HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Exploring the Potential of Error-permissive Communication in Multi-FPGA-based Edge Computing.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

2021
A Multi-Tenant Resource Management System for Multi-FPGA Systems.
IEICE Trans. Inf. Syst., 2021

Remote Dynamic Reconfiguration of a Multi-FPGA System FiC (Flow-in-Cloud).
IEICE Trans. Inf. Syst., 2021

2020
TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Scalable Design Methodology and Online Algorithm for TSV-Cluster Defects Recovery in Highly Reliable 3D-NoC Systems.
IEEE Trans. Emerg. Top. Comput., 2020

Report on power, thermal and reliability prediction for 3D Networks-on-Chip.
CoRR, 2020

A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip.
IEEE Access, 2020

A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems.
IEEE Access, 2020

Horizontal division of deep learning applications with all-to-all communication on a multi-FPGA system.
Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

Implementation of FM-Index Based Pattern Search on a Multi-FPGA System.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

2019
Multi-FPGA Management on Flow-in-Cloud Prototype System.
Proceedings of the 20th IEEE/ACIS International Conference on Software Engineering, 2019

An on-Communication Multiple-TSV Defects Detection and Localization for Real-Time 3D-ICs.
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System.
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

TSV-IaS: Analytic Analysis and Low-Cost Non-Preemptive on-Line Detection and Correction Method for TSV Defects.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Acceleration of Deep Recurrent Neural Networks with an FPGA cluster.
Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2019

Demonstration of Flow-in-Cloud: A Multi-FPGA System.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018
Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

2017
A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Leveraging asymmetric body bias control for low power LSI design.
Proceedings of the 2017 IEEE Symposium in Low-Power and High-Speed Chips, 2017

2016
Adaptive fault-tolerant architecture and routing algorithm for reliable many-core 3D-NoC systems.
J. Parallel Distributed Comput., 2016

Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems.
IEICE Trans. Electron., 2016

MuCCRA4-BB: A fine-grained body biasing capable DRP.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

2015
On the Design of a Fault-Tolerant Photonic Network-on-Chip.
Proceedings of the 2015 IEEE International Conference on Systems, 2015

FTTDOR: Microring Fault-resilient Optical Router for Reliable Optical Network-on-Chip Systems.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

2014
Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures.
J. Parallel Distributed Comput., 2014

Adaptive Error- and Traffic-Aware Router Architecture for 3D Network-on-Chip Systems.
Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014

2013
Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC).
J. Supercomput., 2013

Run-Time Monitoring Mechanism for Efficient Design of Application-Specific NoC Architectures in Multi/Manycore Era.
Proceedings of the Seventh International Conference on Complex, 2013

2012
LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture.
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

ONoC-SPL: Customized Network-on-Chip (NoC) architecture and prototyping for data-intensive computation applications.
Proceedings of the 4th International Conference on Awareness Science and Technology, 2012

Low-overhead Routing Algorithm for 3D Network-on-Chip.
Proceedings of the Third International Conference on Networking and Computing, 2012

2010
Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC.
Proceedings of the Fifth International Conference on Broadband and Wireless Computing, 2010


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