Bert Oude-Essink

According to our database, Bert Oude-Essink authored at least 4 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A 120-MHz BW, 122-dBFS SFDR CTΔΣ ADC With a Multi-Path Multi-Frequency Chopping Scheme.

Sundeep Javvaji, Muhammed Bolatkale, Shagun Bajoria, Robert Rutten, Bert Oude-Essink, Koen Beijens, Kofi A. A. Makinwa, Lucien J. Breems

IEEE J. Solid State Circuits, April, 2024

2023

A 6GHz Multi-Path Multi-Frequency Chopping CTΔΣ Modulator achieving 122dBFS SFDR from 150kHz to 120MHz BW.

Sundeep Javvaji, Muhammed Bolatkale, Shagun Bajoria, Robert Rutten, Bert Oude-Essink, Koen Beijens, Kofi A. A. Makinwa, Lucien J. Breems

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2016

A 2.2 GHz Continuous-Time ΔΣ ADC With -102 dBc THD and 25 MHz Bandwidth.

Lucien J. Breems, Muhammed Bolatkale, Hans Brekelmans, Shagun Bajoria, Jan Niehof, Robert Rutten, Bert Oude-Essink, Franco Fritschij, Jagdip Singh, Gerard Lassche

IEEE J. Solid State Circuits, 2016

15.2 A 2.2GHz continuous-time ΔΣ ADC with -102dBc THD and 25MHz BW.

Lucien J. Breems, Muhammed Bolatkale, Hans Brekelmans, Shagun Bajoria, Jan Niehof, Robert Rutten, Bert Oude-Essink, Franco Fritschij, Jagdip Singh, Gerard Lassche

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016