Robert Rutten

According to our database1, Robert Rutten authored at least 25 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
A 120-MHz BW, 122-dBFS SFDR CTΔΣ ADC With a Multi-Path Multi-Frequency Chopping Scheme.
IEEE J. Solid State Circuits, April, 2024

2023
A 6GHz Multi-Path Multi-Frequency Chopping CTΔΣ Modulator achieving 122dBFS SFDR from 150kHz to 120MHz BW.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022
A 158-mW 360-MHz BW 68-dB DR Continuous-Time 1-1-1 Filtering MASH ADC in 40-nm CMOS.
IEEE J. Solid State Circuits, 2022

A 28-nm 6-GHz 2-bit Continuous-Time ΔΣ ADC With -101-dBc THD and 120-MHz Bandwidth Using Blind Digital DAC Error Correction.
IEEE J. Solid State Circuits, 2022

A 5GS/s 360MHz-BW 68dB-DR Continuous-Time 1-1-1 Filtering MASH ΔΣ ADC in 40nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 28nm 6GHz 2b Continuous-Time ΔΣ ADC with -101 dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 2GHz 2-bit Continuous-Time Delta Sigma ADC with 2GHz chopper achieving 12nV/sqrt(Hz) 1/f noise at 153kHz and -104.7dBc THD in 30MHz BW.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021
A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS.
Proceedings of the 47th ESSCIRC 2021, 2021

2019
A 3.2mW SAR-assisted CTΔ∑ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2017
A 28 nm 2 GS/s 5-b single-channel SAR ADC with gm-boosted StrongARM comparator.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
A 2.2 GHz Continuous-Time ΔΣ ADC With -102 dBc THD and 25 MHz Bandwidth.
IEEE J. Solid State Circuits, 2016

15.2 A 2.2GHz continuous-time ΔΣ ADC with -102dBc THD and 25MHz BW.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain with Carry-Save format numbers.
Microprocess. Microsystems, 2015

2013
A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using Carry-Save format numbers.
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013


2012
A 6.5 GHz Arbitrary Digital Waveform Generator.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
A 4 GHz Continuous-Time ΔΣ ADC With 70 dB DR and -74 dBFS THD in 125 MHz BW.
IEEE J. Solid State Circuits, 2011

A 4GHz CT ΔΣ ADC with 70dB DR and -74dBFS THD in 125MHz BW.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A 45nm WCDMA transmitter using direct quadrature voltage modulator with high oversampling digital front-end.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008
An Inverter-Based Hybrid ΔΣ Modulator.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Digital jitter-cancellation for narrowband signals.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
A 56 mW Continuous-Time Quadrature Cascaded ΣΔ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band.
IEEE J. Solid State Circuits, 2007

A 56mW CT Quadrature Cascaded ΣΔ Modulator with 77dB DR in a Near Zero-IF 20MHz Band.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Continuous-time Sigma-Delta Modulators for Highly Digitised Receivers.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2004
A cascaded continuous-time ΣΔ Modulator with 67-dB dynamic range in 10-MHz bandwidth.
IEEE J. Solid State Circuits, 2004


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