Lucien J. Breems

Orcid: 0000-0001-6984-4162

According to our database1, Lucien J. Breems authored at least 55 papers between 2000 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A 120-MHz BW, 122-dBFS SFDR CTΔΣ ADC With a Multi-Path Multi-Frequency Chopping Scheme.
IEEE J. Solid State Circuits, April, 2024

2023
A 6GHz Multi-Path Multi-Frequency Chopping CTΔΣ Modulator achieving 122dBFS SFDR from 150kHz to 120MHz BW.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022
A 158-mW 360-MHz BW 68-dB DR Continuous-Time 1-1-1 Filtering MASH ADC in 40-nm CMOS.
IEEE J. Solid State Circuits, 2022

A 28-nm 6-GHz 2-bit Continuous-Time ΔΣ ADC With -101-dBc THD and 120-MHz Bandwidth Using Blind Digital DAC Error Correction.
IEEE J. Solid State Circuits, 2022

A 5GS/s 360MHz-BW 68dB-DR Continuous-Time 1-1-1 Filtering MASH ΔΣ ADC in 40nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 28nm 6GHz 2b Continuous-Time ΔΣ ADC with -101 dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 2GHz 2-bit Continuous-Time Delta Sigma ADC with 2GHz chopper achieving 12nV/sqrt(Hz) 1/f noise at 153kHz and -104.7dBc THD in 30MHz BW.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021
A High-Linearity and Low-EMI Multilevel Class-D Amplifier.
IEEE J. Solid State Circuits, 2021

A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS.
Proceedings of the 47th ESSCIRC 2021, 2021

2020
A 28-W, -102.2-dB THD+N Class-D Amplifier Using a Hybrid ΔΣM-PWM Scheme.
IEEE J. Solid State Circuits, 2020

Guest Editorial Special Section on the 45th IEEE European Solid-State Circuits Conference (ESSCIRC).
IEEE J. Solid State Circuits, 2020

A -107.8 dB THD+N Low-EMI Multi-Level Class-D Audio Amplifier.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

23.4 A 28W -108.9dB/-102.2dB THD/THD+N Hybrid ΔΣ-PWM Class-D Audio Amplifier with 91% Peak Efficiency and Reduced EMI Emission.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Analysis of the Inter-Stage Signal Leakage in Wide BW Low OSR and High DR CT MASH ΔΣM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Novel Baseband Analog Beamforming through Resistive DACs and Sigma Delta Modulators.
Proceedings of the European Conference on Circuit Theory and Design, 2020

2019
A 3.2mW SAR-assisted CTΔ∑ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018
A 2 GHz 0.98 mW 4-bit SAR-Based Quantizer with ELD Compensation in an UWB CT ΣΔ Modulator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A Multiphase Class-D Automotive Audio Amplifier With Integrated Low-Latency ADCs for Digitized Feedback After the Output Filter.
IEEE J. Solid State Circuits, 2017

5.1 A 5×80W 0.004% THD+N automotive multiphase Class-D audio amplifier with integrated low-latency ΔΣ ADCs for digitized feedback after the output filter.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Impact of amplifier bandwidth limitations on gain-boosted N-path receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 28 nm 2 GS/s 5-b single-channel SAR ADC with gm-boosted StrongARM comparator.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
A 2.2 GHz Continuous-Time ΔΣ ADC With -102 dBc THD and 25 MHz Bandwidth.
IEEE J. Solid State Circuits, 2016

15.2 A 2.2GHz continuous-time ΔΣ ADC with -102dBc THD and 25MHz BW.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A digital calibration technique for wide-band CT MASH ΣΔ ADCs with relaxed filter requirements.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2014
Introduction to the Special Issue on the 2014 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2014

2011
A 65-nm CMOS Temperature-Compensated Mobility-Based Frequency Reference for Wireless Sensor Networks.
IEEE J. Solid State Circuits, 2011

A 4 GHz Continuous-Time ΔΣ ADC With 70 dB DR and -74 dBFS THD in 125 MHz BW.
IEEE J. Solid State Circuits, 2011

A 4GHz CT ΔΣ ADC with 70dB DR and -74dBFS THD in 125MHz BW.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Effects of packaging and process spread on a mobility-based frequency reference in 0.16-μm CMOS.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010
A 1.2-V 10-μ W NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2°C (3 Sigma ) From - 70°C to 125°C.
IEEE J. Solid State Circuits, 2010

A 200 μA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS.
IEEE J. Solid State Circuits, 2010

A 1.2V 10µW NPN-based temperature sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3s) from -70°C to 125°C.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 2.4GHz 830pJ/bit duty-cycled wake-up receiver with -82dBm sensitivity for crystal-less wireless sensor nodes.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
Impulse-Based Scheme for Crystal-Less ULP Radios.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Special Issue on Circuits and Systems Solutions for Nanoscale CMOS Design Challenges.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios.
IEEE J. Solid State Circuits, 2009

A multi-bit cascaded sigma-delta modulator with an oversampled single-bit DAC.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

A 200 µA duty-cycled PLL for wireless sensor nodes.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
An Inverter-Based Hybrid ΔΣ Modulator.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Digital jitter-cancellation for narrowband signals.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Audio at low and high power.
Proceedings of the ESSCIRC 2008, 2008

2007
An IF-to-Baseband ΣΔ Modulator for AM/FM/IBOC Radio Receivers With a 118 dB Dynamic Range.
IEEE J. Solid State Circuits, 2007

A 56 mW Continuous-Time Quadrature Cascaded ΣΔ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band.
IEEE J. Solid State Circuits, 2007

A 1.2V 121-Mode CT ΔΣ Modulator for Wireless Receivers in 90nm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 56mW CT Quadrature Cascaded ΣΔ Modulator with 77dB DR in a Near Zero-IF 20MHz Band.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
An 118dB DR CT IF-to-Baseband ΣΔ Modulator for AM/FM/IBOC Radio Receivers.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 110dB dynamic range continuous-time IF-to-baseband Sigma Delta modulator for AM/FM/IBOC receivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Noise analysis of continuous-time Sigma Delta modulators with switched-capacitor feedback DAC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Continuous-time Sigma-Delta Modulators for Highly Digitised Receivers.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2004
A cascaded continuous-time ΣΔ Modulator with 67-dB dynamic range in 10-MHz bandwidth.
IEEE J. Solid State Circuits, 2004

2003
IF-to-digital converter for FM/AM/IBOC radio.
Proceedings of the ESSCIRC 2003, 2003

2001
A quadrature data-dependent DEM algorithm to improve image rejection of a complex ΣΔ modulator.
IEEE J. Solid State Circuits, 2001

2000
A 1.8-mW CMOS ΣΔ modulator with integrated mixer for A/D conversion of IF signals.
IEEE J. Solid State Circuits, 2000


  Loading...