Berthold Seger

According to our database, Berthold Seger authored at least 6 papers between 1996 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2012

A high-input-swing common-mode-robust programmable gain amplifier in 65nm CMOS.

Daniel Gruber, Martin Clara, Berthold Seger

Proceedings of the 38th European Solid-State Circuit conference, 2012

2008

A 1.5V 13bit 130-300MS/s self-calibrated DAC with active output stage and 50MHz signal bandwidth in 0.13μm CMOS.

Martin Clara, Wolfgang Klatzer, Daniel Gruber, Arnold Marak, Berthold Seger, Wolfgang Pribyl

Proceedings of the ESSCIRC 2008, 2008

2007

A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13μm CMOS.

Martin Clara, Wolfgang Klatzer, Berthold Seger, Antonio Di Giandomenico, Luca Gori

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2002

A fully integrated analog front-end macro for cable modem applications in 0.18-μm CMOS.

Andreas Wiesbauer, Martin Clara, Moritz Harteneck, Thomas Pötscher, Berthold Seger, Christoph Sandner, Christian Fleischhacker

IEEE J. Solid State Circuits, 2002

An ADSL-RT full-rate analog front end IC with integrated line driver.

Hubert Weinberger, Andreas Wiesbauer, Christian Fleischhacker, Joerg Hauptmann, Thomas Ferianz, Michael Staber, Dietmar Sträußnigg, Berthold Seger

IEEE J. Solid State Circuits, 2002

1996

Fully analogue LMS adaptive notch filter in BICMOS technology.

Thomas Linder, Herbert Zojer, Berthold Seger

IEEE J. Solid State Circuits, 1996