Antonio Di Giandomenico

According to our database1, Antonio Di Giandomenico authored at least 10 papers between 2003 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2015
A multimode CT ΔΣ-modulator with a reconfigurable digital feedback filter for semi-digital blocker/interferer rejection.
Proceedings of the ESSCIRC Conference 2015, 2015

2007
A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13μm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Design of Cascaded Continuous-Time Sigma-Delta Modulators.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2004
A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution.
IEEE J. Solid State Circuits, 2004

Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
A 10-bit, 4 mW continuous-time sigma-delta ADC for UMTS in a 0.12µm CMOS process.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Common mode stability in fully differential voltage feedback CMOS amplifiers.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

A 15 MHz bandwidth sigma-delta ADC with 11 bits of resolution in 0.13μm CMOS.
Proceedings of the ESSCIRC 2003, 2003

10-bit, 3 mW continuous-time sigma-delta ADC for UMTS in a 0.12 μm CMOS process.
Proceedings of the ESSCIRC 2003, 2003


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