Martin Clara

Orcid: 0000-0001-6991-3391

According to our database1, Martin Clara authored at least 17 papers between 2002 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
A 12-b 16-GS/s RF-Sampling Capacitive DAC for Multi-Band Soft Radio Base-Station Applications With On-Chip Transmission-Line Matching Network in 16-nm FinFET.
IEEE J. Solid State Circuits, 2021

10.6 A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

10.7 A 64GS/s 4×-Interpolated 1b Semi-Digital FIR DAC for Wideband Calibration and BIST of RF-Sampling A/D Converters.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2015
A 16-bit 10Gsps current steering RF DAC in 65nm CMOS achieving 65dBc ACLR multi-carrier performance at 4.5GHz Fout.
Proceedings of the Symposium on VLSI Circuits, 2015

2012
A high-input-swing common-mode-robust programmable gain amplifier in 65nm CMOS.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
Jitter Noise of Sampled Multitone Signals.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

2008
A 1.5V 13bit 130-300MS/s self-calibrated DAC with active output stage and 50MHz signal bandwidth in 0.13μm CMOS.
Proceedings of the ESSCIRC 2008, 2008

2007
A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13μm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Clock jitter compensation for current steering DACs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-μm digital CMOS.
IEEE J. Solid State Circuits, 2005

2004
A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution.
IEEE J. Solid State Circuits, 2004

Nonlinear distortion in current-steering D/A-converters due to asymmetrical switching errors.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13μm CMOS.
Proceedings of the 33rd European Solid-State Circuits Conference, 2004

A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13µm Digital CMOS.
Proceedings of the 2004 Design, 2004

Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2002
A fully integrated analog front-end macro for cable modem applications in 0.18-μm CMOS.
IEEE J. Solid State Circuits, 2002

A 1.8 V fully embedded 10 b 160 MS/s two-step ADC in 0.18 μm CMOS.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002


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