Devesh Dwivedi

According to our database1, Devesh Dwivedi authored at least 10 papers between 2012 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Design of Approximate Booth Squarer for Error-Tolerant Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2020

2019
An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM.
Circuits Syst. Signal Process., 2019

2018
Design of Approximate Dividers for Error Tolerant Applications.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2016
A 20 nm robust single-ended boost-less 7T FinFET sub-threshold SRAM cell under process-voltage-temperature variations.
Microelectron. J., 2016

Ultra-Fast Current Mode Sense Amplifier for Small \(I_{\mathrm{CELL}}\) SRAM in FinFET with Improved Offset Tolerance.
Circuits Syst. Signal Process., 2016

Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Design in Sub-threshold Regime for Ultra-Low-Power Applications.
Circuits Syst. Signal Process., 2016

A robust 8T FinFET SRAM cell with improved stability for low voltage applications.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2015
Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small I<sub>cell</sub> SRAM Using FinFET.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014
Single-ended sub-threshold finfet 7T SRAM cell without boosted supply.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

2012
Voltage up level shifter with improved performance and reduced power.
Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012


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