Devesh Dwivedi

According to our database, Devesh Dwivedi authored at least 14 papers between 2012 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process.

Rupesh D. Kadhao, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Devesh Dwivedi

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

ABB Assisted Area Efficient Vernier Delay Line Time-to-Digital Converter for Low Voltage Applications.

Ravi, Lomash Chandra Acharya, Mahipal Dargupally, Neha Gupta, Neeraj Mishra, Lalit Mohan Dani, Nilotpal Sarma, Devesh Dwivedi, Sudeb Dasgupta, Anand Bulusu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2021

Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications.

Karri Manikantta Reddy, M. H. Vasantha, Nithin Y. B. Kumar, Ch. Keshava Gopal, Devesh Dwivedi

Integr., 2021

2020

Design of Approximate Booth Squarer for Error-Tolerant Computing.

Karri Manikantta Reddy, M. H. Vasantha, Nithin Y. B. Kumar, Devesh Dwivedi

IEEE Trans. Very Large Scale Integr. Syst., 2020

2019

An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM.

Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Nand Kishor Yadav, Santosh Kumar Vishvakarma, Devesh Dwivedi

Circuits Syst. Signal Process., 2019

2018

Design of Approximate Dividers for Error Tolerant Applications.

Karri Manikantta Reddy, M. H. Vasantha, Kumar Y. B. Nithin, Devesh Dwivedi

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2016

A 20 nm robust single-ended boost-less 7T FinFET sub-threshold SRAM cell under process-voltage-temperature variations.

C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi

Microelectron. J., 2016

Ultra-Fast Current Mode Sense Amplifier for Small \(I_{\mathrm{CELL}}\) SRAM in FinFET with Improved Offset Tolerance.

Bhupendra Singh Reniwal, Vikas Vijayvargiya, Santosh Kumar Vishvakarma, Devesh Dwivedi

Circuits Syst. Signal Process., 2016

Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Design in Sub-threshold Regime for Ultra-Low-Power Applications.

C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi

Circuits Syst. Signal Process., 2016

A robust 8T FinFET SRAM cell with improved stability for low voltage applications.

C. B. Kushwah, Devesh Dwivedi, N. Sathisha, Krishnan S. Rengarajan

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2015

Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity.

Santosh Kumar Vishvakarma, Bhupendra Singh Reniwal, V. Sharma, C. B. Khuswah, Devesh Dwivedi

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small I_cell SRAM Using FinFET.

Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Santosh Kumar Vishvakarma, Devesh Dwivedi

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014

Single-ended sub-threshold finfet 7T SRAM cell without boosted supply.

C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi

Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

2012

Voltage up level shifter with improved performance and reduced power.

Devesh Dwivedi, Suman Dwivedi, Eswararao Potladhurthi

Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012