Nandakishor Yadav
Orcid: 0000-0002-1849-3224Affiliations:
- Indian Institute of Technology Indore, India
According to our database1,
Nandakishor Yadav
authored at least 15 papers
between 2013 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2023
A comprehensive survey of fake news in social networks: Attributes, features, and detection approaches.
J. King Saud Univ. Comput. Inf. Sci., June, 2023
2022
Eng. Appl. Artif. Intell., 2022
2020
A Novel FPGA Accelerator Design for Real-Time and Ultra-Low Power Deep Convolutional Neural Networks Compared With Titan X GPU.
IEEE Access, 2020
2019
SUBHDIP: process variations tolerant subthreshold Darlington pair-based NBTI sensor circuit.
IET Comput. Digit. Tech., 2019
An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM.
Circuits Syst. Signal Process., 2019
2018
An efficient NBTI sensor and compensation circuit for stable and reliable SRAM cells.
Microelectron. Reliab., 2018
2017
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
2016
Analysis of Single-Trap-Induced Random Telegraph Noise on Asymmetric High-k Spacer FinFET.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016
Investigation of DC Characteristic on DG-Tunnel FET with High-K Dielectric Using Distinct Device Parameter.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016
2015
A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM.
Microelectron. Reliab., 2015
New Topology Approach for Future Process, Voltage and Temperature Aware SRAM Using Independently Controlled Double-Gate FinFET.
J. Low Power Electron., 2015
2014
A New Sensitivity-Driven Process Variation Aware Self-Repairing Low-Power SRAM Design.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Operation-aware assist circuit design for improved write performance of FinFET based SRAM.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
2013
Double-gate FinFET process variation aware 10T SRAM cell topology design and analysis.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013