Arijit Raychowdhury

Orcid: 0000-0001-8391-0576

According to our database1, Arijit Raychowdhury authored at least 231 papers between 2003 and 2024.

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Bibliography

2024
Silent Data Corruption in Robot Operating System: A Case for End-to-End System-Level Fault Analysis Using Autonomous UAVs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking.
IEEE J. Solid State Circuits, January, 2024

Towards Cognitive AI Systems: a Survey and Prospective on Neuro-Symbolic AI.
CoRR, 2024

Twofold Sparsity: Joint Bit- and Network-Level Sparsity for Energy-Efficient Deep Neural Network Using RRAM Based Compute-In-Memory.
IEEE Access, 2024

30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2023

A 90.4% Peak Efficiency 48-to-1-V GaN/Si Hybrid Converter With Three-Level Hybrid Dickson Topology and Gradient Descent Run-Time Optimizer.
IEEE J. Solid State Circuits, 2023

A 2.38 MCells/mm<sup>2</sup> 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

Cryogenic CMOS as an Enabler for Low Power Dynamic Logic.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

Live Demonstration: Hybrid RRAM and SRAM SoC for Fused Frame and Event Target Tracking.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Non-Uniform Interpolation in Integrated Gradients for Low-Latency Explainable-AI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

RAGA: Resource-Aware Tree-Splitting for High Performance Knuth-Yao-based Discrete Gaussian Sampling on FPGAs.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

A Scalable Platform for Single-Snapshot Direction Of Arrival (DOA) Estimation in Massive MIMO Systems.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Real-Time Fully Unsupervised Domain Adaptation for Lane Detection in Autonomous Driving.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

BERRY: Bit Error Robustness for Energy-Efficient Reinforcement Learning-Based Autonomous Systems.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Neuromorphic Swarm on RRAM Compute-in-Memory Processor for Solving QUBO Problem.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

A 65 nm 1.4-6.7 TOPS/W Adaptive-SNR Sparsity-Aware CIM Core with Load Balancing Support for DL workloads.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

Explainable ECG Beat Classification On The Edge for Smart, Trustworthy and Low-Power Wearables.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023

E-Track: Eye Tracking with Event Camera for Extended Reality (XR) Applications.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

PCB Identification Based on Machine Learning Utilizing Power Consumption Variability.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

Reducing Overhead of Feature Importance Visualization via Static GradCAM Computation.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
A Practical Design-Space Analysis of Compute-in-Memory With SRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Design Space Exploration of Interconnect Materials for Cryogenic Operation: Electrical and Thermal Analyses.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

BitS-Net: Bit-Sparse Deep Neural Network for Energy-Efficient RRAM-Based Compute-In-Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

An End-to-End Spiking Neural Network Platform for Edge Robotics: From Event-Cameras to Central Pattern Generation.
IEEE Trans. Cogn. Dev. Syst., 2022

A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding.
IEEE J. Solid State Circuits, 2022

A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection.
IEEE J. Solid State Circuits, 2022

A 65 nm Wireless Image SoC Supporting On-Chip DNN Optimization and Real-Time Computation-Communication Trade-Off via Actor-Critical Neuro-Controller.
IEEE J. Solid State Circuits, 2022

EM-X-DL: Efficient Cross-device Deep Learning Side-channel Attack With Noisy EM Signatures.
ACM J. Emerg. Technol. Comput. Syst., 2022

A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link.
Integr., 2022

Circuit and System Technologies for Energy-Efficient Edge Robotics.
CoRR, 2022

A 90.4% Peak Efficiency 48V/1V Three-Level Hybrid Dickson Converter with Gradient Descent Run-Time Optimizer and GaN/Si Hybrid Conversion.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Towards CIM-friendly and Energy-Efficient DNN Accelerator via Bit-level Sparsity.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Towards Energy Efficient DNN accelerator via Sparsified Gradual Knowledge Distillation.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Gradient Backpropagation based Feature Attribution to Enable Explainable-AI on the Edge.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

A 40nm 64kb 26.56TOPS/W 2.37Mb/mm<sup>2</sup>RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Fusing Frame and Event Vision for High-speed Optical Flow for Edge Application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Characterization and Mitigation of IR-Drop in RRAM-based Compute In-Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

RAPID-RL: A Reconfigurable Architecture with Preemptive-Exits for Efficient Deep-Reinforcement Learning.
Proceedings of the 2022 International Conference on Robotics and Automation, 2022

Analyzing and Improving Resilience and Robustness of Autonomous Systems.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Exploration into the Explainability of Neural Network Models for Power Side-Channel Analysis.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

FRL-FI: Transient Fault Analysis for Federated Reinforcement Learning-Based Navigation Systems.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Improving compute in-memory ECC reliability with successive correction.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

An Energy-Efficient and Runtime-Reconfigurable FPGA-Based Accelerator for Robotic Localization Systems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

An Analog Clock-free Compute Fabric base on Continuous-Time Dynamical System for Solving Combinatorial Optimization Problems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

Circuit and System Technologies for Energy-Efficient Edge Robotics: (Invited Paper).
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

Robotic Computing on FPGAs: Current Progress, Research Challenges, and Opportunities.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
A 65nm Thermometer-Encoded Time/Charge-Based Compute-in-Memory Neural Network Accelerator at 0.735pJ/MAC and 0.41pJ/Update.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Hardware-Friendly Approach Towards Sparse Neural Networks Based on LFSR-Generated Pseudo-Random Sequences.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

NeuroSLAM: A 65-nm 7.25-to-8.79-TOPS/W Mixed-Signal Oscillator-Based SLAM Accelerator for Edge Robotics.
IEEE J. Solid State Circuits, 2021

EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing.
IEEE J. Solid State Circuits, 2021

EM/Power Side-Channel Attack: White-Box Modeling and Signature Attenuation Countermeasures.
IEEE Des. Test, 2021

Merged Logic and Memory Fabrics for Accelerating Machine Learning Workloads.
IEEE Des. Test, 2021

MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles.
CoRR, 2021

Multi-Task Federated Reinforcement Learning with Adversaries.
CoRR, 2021

A decentralized policy gradient approach to multi-task reinforcement learning.
Proceedings of the Thirty-Seventh Conference on Uncertainty in Artificial Intelligence, 2021

29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Session 35 Overview: Adaptive Digital Techniques for Variation Tolerant Systems Digital Circuits Subcommittee.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

F3: Silicon Technologies in the Fight Against Pandemics - From Point of Care to Computational Epidemiology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

F4: Electronics for a Quantum World.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Automatic Generation of Translators for Packet-Based and Emerging Protocols.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Statistical Optimization of Compute In-Memory Performance Under Device Variation.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

Analyzing and Improving Fault Tolerance of Learning-Based Navigation Systems.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and Performance.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

CryoMem: A 4K-300K 1.3GHz eDRAM Macro with Hybrid 2T-Gain-Cell in a 28nm Logic Process for Cryogenic Applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

Merged Logic and Memory Fabrics for AI Workloads.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

An Energy-Efficient Quad-Camera Visual System for Autonomous Machines on FPGA Platform.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

iELAS: An ELAS-Based Energy-Efficient Accelerator for Real-Time Stereo Matching on FPGA Platform.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

Hardware-Algorithm Co-Design Enabling Efficient Event-based Object Detection.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020
FerroElectronics for Edge Intelligence.
IEEE Micro, 2020

OPTIMO: A 65-nm 279-GOPS/W 16-b Programmable Spatial-Array Processor with On-Chip Network for Solving Distributed Optimizations via the Alternating Direction Method of Multipliers.
IEEE J. Solid State Circuits, 2020

A 65-nm 8-to-3-b 1.0-0.36-V 9.1-1.1-TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Swarm Robotics.
IEEE J. Solid State Circuits, 2020

120.147 Efficient Electromagnetic Side Channel Analysis by Probe Positioning using Multi-Layer Perceptron.
IACR Cryptol. ePrint Arch., 2020

Learning to Walk: Bio-Mimetic Hexapod Locomotion via Reinforcement-Based Spiking Central Pattern Generation.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020

A Survey of FPGA-Based Robotic Computing.
CoRR, 2020

Masked Face Recognition for Secure Authentication.
CoRR, 2020

Counting Cards: Exploiting Weight and Variance Distributions for Robust Compute In-Memory.
CoRR, 2020

SCNIFFER: Low-Cost, Automated, Efficient Electromagnetic Side-Channel Sniffing.
IEEE Access, 2020

Autonomous Navigation via Deep Reinforcement Learning for Resource Constraint Edge Nodes Using Transfer Learning.
IEEE Access, 2020

A 65nm Image Processing SoC Supporting Multiple DNN Models and Real-Time Computation-Communication Trade-Off Via Actor-Critical Neuro-Controller.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication.
Proceedings of the VLSI-SoC: Design Trends, 2020

A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Online Reward-Based Training of Spiking Central Pattern Generator for Hexapod Locomotion.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Memory and Energy Efficient Method Toward Sparse Neural Network Using LFSR Indexing.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics.
Proceedings of the VLSI-SoC: Design Trends, 2020

Breaking Barriers: Maximizing Array Utilization for Compute in-Memory Fabrics.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Non-isolated 48V-to-1V Heterogeneous Integrated Voltage Converters for High Performance Computing in Data Centers.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

31.1 A 65nm 8.79TOPS/W 23.82mW Mixed-Signal Oscillator-Based NeuroSLAM Accelerator for Applications in Edge Robotics.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

27.3 EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Hardware-Aware Pruning of DNNs using LFSR-Generated Pseudo-Random Indices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Quad-Output Elastic Switched Capacitor Converter and Per-Core LDO with 87% Power Efficiency and 2.5× Core-Frequency Range Improvement.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Bio-inspired Gait Imitation of Hexapod Robot Using Event-Based Vision Sensor and Spiking Neural Network.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

Deep Learning Side-Channel Attack Resilient AES-256 using Current Domain Signature Attenuation in 65nm CMOS.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

Learning to Walk: Spike Based Reinforcement Learning for Hexapod Robot Central Pattern Generation.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

XBAROPT - Enabling Ultra-Pipelined, Novel STT MRAM Based Processing-in-Memory DNN Accelerator.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019
Practical Approaches Toward Deep-Learning-Based Cross-Device Power Side-Channel Attack.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Computing With Networks of Oscillatory Dynamical Systems.
Proc. IEEE, 2019

A 55-nm, 1.0-0.4V, 1.25-pJ/MAC Time-Domain Mixed-Signal Neuromorphic Accelerator With Stochastic Synapses for Reinforcement Learning in Autonomous Mobile Robots.
IEEE J. Solid State Circuits, 2019

X-DeepSCA: Cross-Device Deep Learning Side Channel Attack.
IACR Cryptol. ePrint Arch., 2019

Hierarchical Memory System With STT-MRAM and SRAM to Support Transfer and Real-Time Reinforcement Learning in Autonomous Drones.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Guest Editors' Introduction: Intelligent Resource-Constrained Sensor Nodes.
IEEE Des. Test, 2019

Context-Aware Intelligence in Resource-Constrained IoT Nodes: Opportunities and Challenges.
IEEE Des. Test, 2019

SCNIFFER: Low-Cost, Automated, EfficientElectromagnetic Side-Channel Sniffing.
CoRR, 2019

Design space exploration of Ferroelectric FET based Processing-in-Memory DNN Accelerator.
CoRR, 2019

Direct Feedback Alignment with Sparse Connections for Local Learning.
CoRR, 2019

A 7nm Leakage-Current-Supply Circuit for LDO Dropout Voltage Reduction.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 65nm 1.1-to-9.1TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Model-Based and Model-Free Swarm Robotics.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Local Learning in RRAM Neural Networks with Sparse Direct Feedback Alignment.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Efficient Signal Reconstruction via Distributed Least Square Optimization on a Systolic FPGA Architecture.
Proceedings of the IEEE International Conference on Acoustics, 2019

Transfer and Online Reinforcement Learning in STT-MRAM Based Embedded Systems for Autonomous Drones.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Rebooting Our Computing Models.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

A 55nm 50nJ/encode 13nJ/decode Homomorphic Encryption Crypto-Engine for IoT Nodes to Enable Secure Computation on Encrypted Data.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

Optimo: A 65Nm 270Mhz 143.2Mw Programmable Spatial-Array-Processor With A Hierarchical Multi-Cast On-Chip Network For Solving Distributed Optimizations.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
Smart Sensing for HVAC Control: Collaborative Intelligence in Optical and IR Cameras.
IEEE Trans. Ind. Electron., 2018

A Light-Powered Smart Camera With Compressed Domain Gesture Detection.
IEEE Trans. Circuits Syst. Video Technol., 2018

A Reconfigurable Hybrid Low Dropout Voltage Regulator for Wide-Range Power Supply Noise Rejection and Energy-Efficiency Trade-Off.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

ASNI: Attenuated Signature Noise Injection for Low-Overhead Power Side-Channel Attack Immunity.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 130 nm 165 nJ/frame Compressed-Domain Smashed-Filter-Based Mixed-Signal Classifier for "In-Sensor" Analytics in Smart Cameras.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Modeling and Analysis of Magnetic Field Induced Coupling on Embedded STT-MRAM Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Switched-Mode-Control Based Hybrid LDO for Fine-Grain Power Management of Digital Load Circuits.
IEEE J. Solid State Circuits, 2018

Dynamics of Coupled Systems and their Computing Properties Invited Paper : Invited Paper.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

NavREn-Rl: Learning to fly in real environment via end-to-end deep reinforcement learning using monocular images.
Proceedings of the 25th International Conference on Mechatronics and Machine Vision in Practice, 2018

A 55nm time-domain mixed-signal neuromorphic accelerator with stochastic synapses and embedded reinforcement learning for autonomous micro-robots.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 65nm, 1.15-0.15V, 99.99% Current-efficient Digital Low Dropout Regulator with Asynchronous Non-linear Control for Droop Mitigation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Computing with Coupled Oscillators: Theory, Devices, and Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A FeFET Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations.
Proceedings of the 76th Device Research Conference, 2018

2017
Self-Optimizing IoT Wireless Video Sensor Node With In-Situ Data Analytics and Context-Driven Energy-Aware Real-Time Adaptation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Stochastic IMT (insulator-metal-transition) neurons: An interplay of thermal and threshold noise at bifurcation.
CoRR, 2017

Innovative practices session 4A variation-tolerant design of circuits/systems.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Test challenges in embedded STT-MRAM arrays.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Computational paradigms using oscillatory networks based on state-transition devices.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Collaborative intelligence in optical/IR camera based wireless sensor nodes for HVAC control.
Proceedings of the 2017 IEEE SENSORS, Glasgow, United Kingdom, October 29, 2017

Connecting spectral techniques for graph coloring and eigen properties of coupled dynamics: A pathway for solving combinatorial optimizations (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Appearance-based gesture recognition in the compressed domain.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

High efficiency power side-channel attack immunity using noise injection in attenuated signature domain.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

In Quest of the Next Information Processing Substrate: Extended Abstract: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

Digitally-assisted leakage current supply circuit for reducing the analog LDO minimum dropout voltage.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 65nm compressive-sensing time-based ADC with embedded classification and INL-aware training for arrhythmia detection.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Test and Reliability of Emerging Non-volatile Memories.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

A 65nm 376nA 0.4V linear classifier using time-based matrix-multiplying ADC with non-linearity aware training.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
Enabling New Computation Paradigms with HyperFET - An Emerging Device.
IEEE Trans. Multi Scale Comput. Syst., 2016

Cache Design with Domain Wall Memory.
IEEE Trans. Computers, 2016

Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

The Changing Computing Paradigm With Internet of Things: A Tutorial Introduction.
IEEE Des. Test, 2016

Vertex coloring of graphs via phase dynamics of coupled oscillatory networks.
CoRR, 2016

Computing with Dynamical Systems Based on Insulator-Metal-Transition Oscillators.
CoRR, 2016

EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays.
Proceedings of the 2016 IEEE International Test Conference, 2016

A Light-powered, "Always-On", Smart Camera with Compressed Domain Gesture Detection.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

All-digital linear regulators with proactive and reactive gain-boosting for supply droop mitigation in digital load circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A 130nm hybrid low dropout regulator based on switched mode control for digital load circuits.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

UVFR: A Unified Voltage and Frequency Regulator with 500MHz/0.84V to 100KHz/0.27V operating range, 99.4% current efficiency and 27% supply guardband reduction.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Embedded hybrid LDO topologies for digital load circuits.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
An Ultra-Low Power, "Always-On" Camera Front-End for Posture Detection in Body Worn Cameras Using Restricted Boltzman Machines.
IEEE Trans. Multi Scale Comput. Syst., 2015

Modeling and Simulation of Vanadium Dioxide Relaxation Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A Model Study of an All-Digital, Discrete-Time and Embedded Linear Regulator.
CoRR, 2015

A SAR Pipeline ADC Embedding Time Interleaved DAC Sharing for Ultra-low Power Camera Front Ends.
Proceedings of the VLSI-SoC: Design for Reliability, Security, and Low Power, 2015

A time interleaved DAC sharing SAR Pipeline ADC for ultra-low power camera front ends.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

5.6 A 0.13μm fully digital low-dropout regulator with adaptive control and reduced dynamic stability for ultra-wide dynamic range.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Integrated power management in IoT devices under wide dynamic ranges of operation.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Session 6 - Analog circuits using digital cells.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits.
IEEE J. Solid State Circuits, 2014

Exploiting Synchronization Properties of Correlated Electron Devices in a Non-Boolean Computing Fabric for Template Matching.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Modeling and analysis of system stability in a distributed power delivery network with embedded digital linear regulators.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

The role of adaptation and resiliency in computation and power management.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Modeling and analysis of digital linear dropout regulators with adaptive control for high efficiency under wide dynamic range digital loads.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Neuro Inspired Computing with Coupled Relaxation Oscillators.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
A 2.3 nJ/Frame Voice Activity Detector-Based Audio Front-End for Context-Aware System-On-Chip Applications in 32-nm CMOS.
IEEE J. Solid State Circuits, 2013

Introduction to the special issue on memory technologies.
ACM J. Emerg. Technol. Comput. Syst., 2013

Pulsed READ in spin transfer torque (STT) memory bitcell for lower READ disturb.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Beyond charge based computation: Design space exploration of spin transfer torque based MRAMs for embedded applications.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Spin torque devices in embedded memory: model studies and design space exploration.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012
A fully-digital phase-locked low dropout regulator in 32nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

TapeCache: a high density, energy efficient cache based on domain wall memory.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Design for test and reliability in ultimate CMOS.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A 2.3nJ/frame Voice Activity Detector based audio front-end for context-aware System-on-Chip applications in 32nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays.
IEEE J. Solid State Circuits, 2011

A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance.
IEEE J. Solid State Circuits, 2011

Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges.
Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

2010
Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device-Circuit-Architecture Codesign Perspective.
Proc. IEEE, 2010

Optimization of burn-in test for many-core processors through adaptive spatiotemporal power migration.
Proceedings of the 2011 IEEE International Test Conference, 2010

A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Resilient microprocessor design for high performance & energy efficiency.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Resilient design in scaled CMOS for energy efficiency.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
A 1.05 V 1.6 mW, 0.45°C 3σ Resolution ΣΔ Based Temperature Sensor With Parasitic Resistance Compensation in 32 nm Digital CMOS Process.
IEEE J. Solid State Circuits, 2009

A 1.05V 1.6mW 0.45°C 3σ-resolution ΔΣ-based temperature sensor with parasitic-resistance compensation in 32nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique.
J. Electron. Test., 2008

2007
Carbon Nanotube Electronics: Design of High-Performance and Low-Power Digital Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

2006
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Leakage Power Analysis and Reduction for Nanoscale Circuits.
IEEE Micro, 2006

Analysis of super cut-off transistors for ultralow power digital logic circuits.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A high density, carbon nanotube capacitor for decoupling applications.
Proceedings of the 43rd Design Automation Conference, 2006

Integrated MEMS Switches for Leakage Control of Battery Operated Systems.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Energy-Recovery Techniques to Reduce On-Chip Power Density in Molecular Nanotechnologies.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current.
J. Electron. Test., 2005

Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current.
J. Electron. Test., 2005

A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

A Feasibility Study of Subthreshold SRAM Across Technology Generations.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points.
Proceedings of the 10th European Test Symposium, 2005

A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application.
Proceedings of the 2005 Design, 2005

Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
A circuit-compatible model of ballistic carbon nanotube field-effect transistors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Modeling and Estimation of Leakage in Sub-90nm Devices.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

Device optimization for ultra-low power digital sub-threshold operation.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis.
Proceedings of the 2004 Design, 2004

2003
Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling.
Proceedings of the 40th Design Automation Conference, 2003


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