Vikram Iyengar

According to our database, Vikram Iyengar authored at least 46 papers between 1997 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2012

Physically-Aware N-Detect Test.

Yen-Tzu Lin, Osei Poku, R. D. (Shawn) Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2010

Low cost at-speed testing using On-Product Clock Generation compatible with test compression.

Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise

Proceedings of the 2011 IEEE International Test Conference, 2010

2009

Wafer-Level Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs.

Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar

IEEE Trans. Very Large Scale Integr. Syst., 2009

2008

Evaluating the Effectiveness of Physically-Aware N-Detect Test using Real Silicon.

Yen-Tzu Lin, Osei Poku, Ronald D. Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar

Proceedings of the 2008 IEEE International Test Conference, 2008

2007

An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs.

Vikram Iyengar, Kenneth Pichamuthu, Andrew Ferko, Frank Woytowich, David E. Lackey, Gary Grise, Mark Taylor, Mike Degregorio, Steven F. Oakland

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Variation-aware performance verification using at-speed structural test and statistical timing.

Vikram Iyengar, Jinjun Xiong, Subbayyan Venkatesan, Vladimir Zolotov, David E. Lackey, Peter A. Habitz, Chandu Visweswariah

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs.

Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking.

Chunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

At-Speed Structural Test For High-Performance ASICs.

Vikram Iyengar, Toshihiko Yokota, Kazuhiro Yamada, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Mark Johnson, Dave Milton, Mark Taylor, Frank Woytowich

Proceedings of the 2006 IEEE International Test Conference, 2006

Performance verification of high-performance ASICs using at-speed structural test.

Vikram Iyengar, Mark Johnson, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Phil Stevens, Mark Taylor, Frank Woytowich

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking.

Chunsheng Liu, Vikram Iyengar

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A flexible and scalable methodology for GHz-speed structural test.

Vikram Iyengar, Gary Grise, Mark Taylor

Proceedings of the 43rd Design Automation Conference, 2006

Design For At-Speed Structural Test And Performance Verification Of High-Performance ASICs.

Vikram Iyengar, Mark Johnson, Theo Anemikos, Gary Grise, Mark Taylor, Raymond Farmer, Frank Woytowich, Bob Bassett

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

Test planning for modular testing of hierarchical SOCs.

Krishnendu Chakrabarty, Vikram Iyengar, Mark D. Krasniewski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking.

Chunsheng Liu, Vikram Iyengar, Jiangfan Shi, Érika F. Cota

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

User interfaces for continuum robot arms.

Matthew A. Csencsits, Bryan A. Jones, William McMahan, Vikram Iyengar, Ian D. Walker

Proceedings of the 2005 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2005

Thermal-Aware Test Scheduling and Hot Spot Temperature Minimization for Core-Based Systems.

Chunsheng Liu, Kugesh Veeraraghavant, Vikram Iyengar

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Defect-Oriented Test for Ultra-Low DPM.

Vikram Iyengar, Phil Nigh

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

SOC test planning using virtual test access architectures.

Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty

IEEE Trans. Very Large Scale Integr. Syst., 2004

2003

Efficient test access mechanism optimization for system-on-chip.

Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip.

Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen

IEEE Trans. Computers, 2003

Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs.

Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Krasniewski, Gopind N. Kumar

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

A Uni.ed SOC Test Approach Based on Test Data Compression and TAM Design.

Vikram Iyengar, Anshuman Chandra

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization.

Vikram Iyengar, Anshuman Chandra, Sharon Schweizer, Krishnendu Chakrabarty

Proceedings of the 2003 Design, 2003

Test cost reduction for SOCs using virtual TAMs and lagrange multipliers.

Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty

Proceedings of the 40th Design Automation Conference, 2003

2002

System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints.

Vikram Iyengar, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Test Bus Sizing for System-on-a-Chip.

Vikram Iyengar, Krishnendu Chakrabarty

IEEE Trans. Computers, 2002

Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip.

Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen

J. Electron. Test., 2002

On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization.

Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

A Set of Benchmarks fo Modular Testing of SOCs.

Erik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

On the Use of k-tuples for SoC Test Schedule Representation.

Sandeep Koranne, Vikram Iyengar

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints.

Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Efficient Wrapper/TAM Co-Optimization for Large SOCs.

Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen

Proceedings of the 2002 Design, 2002

Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs.

Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen

Proceedings of the 39th Design Automation Conference, 2002

Recent Advances in Test Planning for Modular Testing of Core-Based SOCs.

Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Test Resource Partitioning for System-on-a-Chip.

Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra

Frontiers in electronic testing 20, Kluwer / Springer, ISBN: 978-1-4020-7119-5, 2002

2001

Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip.

Vikram Iyengar, Krishnendu Chakrabarty

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

2000

Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters.

Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar

IEEE Trans. Very Large Scale Integr. Syst., 2000

A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors.

Ta-Chung Chang, Vikram Iyengar, Elizabeth M. Rudnick

J. Electron. Test., 2000

Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores.

Hiroshi Date, Vikram Iyengar, Krishnendu Chakrabarty, Makoto Sugihara

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

1999

Microprocessor Design Verification.

Vikram Iyengar, Elizabeth M. Rudnick

Proceedings of the VLSI Handbook., 1999

Deterministic Built-in Pattern Generation for Sequential Circuits.

Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray

J. Electron. Test., 1999

Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters.

Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

1998

Huffman encoding of test sets for sequential circuits.

Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray

IEEE Trans. Instrum. Meas., 1998

Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets.

Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

1997

An Efficient Finite-State Machine Implementation of Huffman Decoders.

Vikram Iyengar, Krishnendu Chakrabarty

Inf. Process. Lett., 1997