Vikram Iyengar

According to our database1, Vikram Iyengar authored at least 46 papers between 1997 and 2012.

Collaborative distances:



In proceedings 
PhD thesis 




Physically-Aware N-Detect Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Low cost at-speed testing using On-Product Clock Generation compatible with test compression.
Proceedings of the 2011 IEEE International Test Conference, 2010

Wafer-Level Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Evaluating the Effectiveness of Physically-Aware N-Detect Test using Real Silicon.
Proceedings of the 2008 IEEE International Test Conference, 2008

An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Variation-aware performance verification using at-speed structural test and statistical timing.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

At-Speed Structural Test For High-Performance ASICs.
Proceedings of the 2006 IEEE International Test Conference, 2006

Performance verification of high-performance ASICs using at-speed structural test.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A flexible and scalable methodology for GHz-speed structural test.
Proceedings of the 43rd Design Automation Conference, 2006

Design For At-Speed Structural Test And Performance Verification Of High-Performance ASICs.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Test planning for modular testing of hierarchical SOCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

User interfaces for continuum robot arms.
Proceedings of the 2005 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2005

Thermal-Aware Test Scheduling and Hot Spot Temperature Minimization for Core-Based Systems.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Defect-Oriented Test for Ultra-Low DPM.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

SOC test planning using virtual test access architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Efficient test access mechanism optimization for system-on-chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip.
IEEE Trans. Computers, 2003

Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

A Uni.ed SOC Test Approach Based on Test Data Compression and TAM Design.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization.
Proceedings of the 2003 Design, 2003

Test cost reduction for SOCs using virtual TAMs and lagrange multipliers.
Proceedings of the 40th Design Automation Conference, 2003

System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Test Bus Sizing for System-on-a-Chip.
IEEE Trans. Computers, 2002

Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip.
J. Electron. Test., 2002

On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

A Set of Benchmarks fo Modular Testing of SOCs.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

On the Use of k-tuples for SoC Test Schedule Representation.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Efficient Wrapper/TAM Co-Optimization for Large SOCs.
Proceedings of the 2002 Design, 2002

Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs.
Proceedings of the 39th Design Automation Conference, 2002

Recent Advances in Test Planning for Modular Testing of Core-Based SOCs.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Test Resource Partitioning for System-on-a-Chip.
Frontiers in electronic testing 20, Kluwer / Springer, ISBN: 978-1-4020-7119-5, 2002

Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters.
IEEE Trans. Very Large Scale Integr. Syst., 2000

A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors.
J. Electron. Test., 2000

Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

Microprocessor Design Verification.
Proceedings of the VLSI Handbook., 1999

Deterministic Built-in Pattern Generation for Sequential Circuits.
J. Electron. Test., 1999

Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Huffman encoding of test sets for sequential circuits.
IEEE Trans. Instrum. Meas., 1998

Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

An Efficient Finite-State Machine Implementation of Huffman Decoders.
Inf. Process. Lett., 1997