ByongChan Lim

According to our database, ByongChan Lim authored at least 9 papers between 2009 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

Open-Source Synthesizable Analog Blocks for High-Speed Link Designs: 20-GS/s 5b ENOB Analog-to-Digital Converter and 5-GHz Phase Interpolator.

Sung-Jin Kim, Zachary Myers, Steven Herbst, ByongChan Lim, Mark Horowitz

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019

An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal Design Verification.

ByongChan Lim, Mark Horowitz

IEEE Trans. Very Large Scale Integr. Syst., 2019

2018

Fast FPGA emulation of analog dynamics in digitally-driven systems.

Steven Herbst, ByongChan Lim, Mark Horowitz

Proceedings of the International Conference on Computer-Aided Design, 2018

2016

Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models.

ByongChan Lim, Mark Horowitz

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 220pJ/pixel/frame CMOS image sensor with partial settling readout architecture.

Suyao Ji, Jing Pu, ByongChan Lim, Mark Horowitz

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015

Digital Analog Design: Enabling Mixed-Signal System Validation.

ByongChan Lim, Ji-Eun Jang, James Mao, Jaeha Kim, Mark Horowitz

IEEE Des. Test, 2015

2010

An efficient test vector generation for checking analog/mixed-signal functional models.

ByongChan Lim, Jaeha Kim, Mark A. Horowitz

Proceedings of the 47th Design Automation Conference, 2010

Fortifying analog models with equivalence checking and coverage analysis.

Mark Horowitz, Metha Jeeradit, Frances Lau, Sabrina Liao, ByongChan Lim, James Mao

Proceedings of the 47th Design Automation Conference, 2010

2009

Leveraging designer's intent: A path toward simpler analog CAD tools.

Jaeha Kim, Metha Jeeradit, ByongChan Lim, Mark A. Horowitz

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009