Metha Jeeradit

According to our database1, Metha Jeeradit authored at least 10 papers between 2003 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2010
Nano-magnetic non-volatile CMOS circuits for nano-scale FPGAs (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Intent-leveraged optimization of analog circuits via homotopy.
Proceedings of the Design, Automation and Test in Europe, 2010

Fortifying analog models with equivalence checking and coverage analysis.
Proceedings of the 47th Design Automation Conference, 2010

2009
Leveraging designer's intent: A path toward simpler analog CAD tools.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications.
IEEE J. Solid State Circuits, 2008

A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter.
IEEE J. Solid State Circuits, 2008

Impulse sensitivity function analysis of periodic circuits.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005
Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2003
Compressing Extended Program Traces Using Value Predictors.
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003


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