Jaeha Kim

Orcid: 0000-0003-2237-3134

According to our database1, Jaeha Kim authored at least 92 papers between 2000 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
Beyond Image Super-Resolution for Image Recognition with Task-Driven Perceptual Loss.
CoRR, 2024

2023
Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test Circuits.
IEEE Access, 2023

Reachability Analysis for Nonlinear Analog/Mixed-Signal Circuits With Trajectory-Based Reachable Sets.
IEEE Access, 2023

Recovering 3D Hand Mesh Sequence from a Single Blurry Image: A New Dataset and Temporal Unfolding.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

2022
A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Toward Real-World Super-Resolution via Adaptive Downsampling Models.
IEEE Trans. Pattern Anal. Mach. Intell., 2022

Seemo: A new tool for early design window view satisfaction evaluation in residential buildings.
CoRR, 2022

XSNN: a System-Level Simulator for Spiking Neural Network with Neuron Circuits and Synapse Devices.
Proceedings of the 19th International SoC Design Conference, 2022

A Gradient-Descent Calibration Method to Mitigate Process Variations in Analog Synapse Arrays.
Proceedings of the International Conference on Electronics, Information, and Communication, 2022

2021
A Time-Based Pipelined ADC Using Integrate-and-Fire Multiplying-DAC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Safety Verification of AMS Circuits with Piecewise-Linear System Reachability Analysis.
Proceedings of the 18th International SoC Design Conference, 2021

Fast Automatic Circuit Optimization Using Deep Learning.
Proceedings of the 18th International SoC Design Conference, 2021

2020
Modeling and Simulation of NAND Flash Memory Sensing Systems with Cell-to-Cell Vth Variations.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 2 × Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery.
IEEE J. Solid State Circuits, 2019

A channel-emulating high-speed transmitter with pseudo-logarithmic and low-bandwidth amplifiers.
IEICE Electron. Express, 2019

2018
Design and Analysis of Energy-Efficient Single-Pulse Piezoelectric Energy Harvester and Power Management IC for Battery-Free Wireless Remote Switch Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Electronic skins for soft, compact, reversible assembly of wirelessly activated fully soft robots.
Sci. Robotics, 2018

CHIMERA: A Field-Programmable Mixed-Signal IC With Time-Domain Configurable Analog Blocks.
IEEE J. Solid State Circuits, 2018

EE6: Can artificial intelligence replace my job? The dawn of a new IC industry with AI.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
Introduction to the Special Section on the 2016 Asian Solid-State Circuits Conference (A-SSCC 2016).
IEEE J. Solid State Circuits, 2017

Compensation of perceived hardness of a virtual object with cutaneous feedback.
Proceedings of the 2017 IEEE World Haptics Conference, 2017

Adaptive vibrotactile flow rendering of 2.5D surface features on touch screen with multiple fingertip interfaces.
Proceedings of the 2017 IEEE World Haptics Conference, 2017

2016
Efficient Global Optimization of Analog Circuits Using Predictive Response Surface Models on Discretized Design Space.
IEEE Des. Test, 2016

A field-programmable mixed-signal IC with time-domain configurable analog blocks.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

13.1 A 940MHz-bandwidth 28.8µs-period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Session 10 overview: Advanced wireline transceivers and PLLs.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Rendering Moving Tactile Stroke on the Palm Using a Sparse 2D Array.
Proceedings of the Haptics: Perception, Devices, Control, and Applications, 2016

Time slot optimization algorithm for multisource energy harvesting systems.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
Depth Cube-Based Six Degree-of-Freedom Haptic Rendering for Rigid Bodies.
IEEE Trans. Haptics, 2015

PPV-Based Modeling and Event-Driven Simulation of Injection-Locked Oscillators in SystemVerilog.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Jussi Ryynänen Introduction to the December Special Issue on the 2015 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2015

Digital Analog Design: Enabling Mixed-Signal System Validation.
IEEE Des. Test, 2015

A 2.5-V, 160-μJ-output piezoelectric energy harvester and power management IC for batteryless wireless switch (BWS) applications.
Proceedings of the Symposium on VLSI Circuits, 2015

The contact/non-contact thimble haptic device.
Proceedings of the IEEE International Conference on Mechatronics, 2015

2014
Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Yield-Aware Pareto Front Extraction for Discrete Hierarchical Optimization of Analog Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Variability-Aware, Discrete Optimization for Analog Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function.
IEEE J. Solid State Circuits, 2014

A built-in self-test circuit for jitter tolerance measurement in high-speed wireline receivers.
Proceedings of the 2014 International Test Conference, 2014

Probabilistic Bug Localization via Statistical Inference based on Partially Observed Data.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

PPV-based modeling and event-driven simulation of injection-locked oscillators in SystemVerilog.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Advanced modeling and simulation of state-of-the-art high-speed I/O interfaces.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Preventing Global Convergence Failure in Mixed-Signal Systems via Indeterminate State ('X') Elimination.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Pseudo-Linear Analysis of Bang-Bang Controlled Timing Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Construction of a haptic-enabled broadcasting system based on the MPEG-V standard.
Signal Process. Image Commun., 2013

A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm.
IEEE J. Solid State Circuits, 2013

A low-power high-radix switch fabric based on low-swing signaling and partially-activated input lines.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Robust random chip ID generation with wide-aperture clocked comparators and maximum likelihood detection.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Verifying start-up failures in coupled ring oscillators in presence of variability using predictive global optimization.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

MPEG-V standardization for haptically interacting with virtual worlds.
Proceedings of the 2013 World Haptics Conference, 2013

An event-driven simulation methodology for integrated switching power supplies in SystemVerilog.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Discretization and discrimination methods for design, verification, and testing of analog/mixed-signal circuits.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Event-driven simulation of Volterra series models in SystemVerilog.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Wireline transmitter and receiver design techniques.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Memory-centric system interconnect design with Hybrid Memory Cubes.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
Design of low-power high-radix switch fabric with partially-activated input and output lines.
Proceedings of the International SoC Design Conference, 2012

A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Variability-aware, discrete optimization for analog circuits.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

A 5-Gbps 1.7 pJ/bit ditherless CDR with optimal phase interval detection.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

True event-driven simulation of analog/mixed-signal behaviors in SystemVerilog: A decision-feedback equalizing (DFE) receiver example.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Global convergence analysis of mixed-signal systems.
Proceedings of the 48th Design Automation Conference, 2011

Fast and accurate event-driven simulation of mixed-signal systems with data supplementation.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Enhancing rate-hardness of energy-bounding algorithm by considering Coulomb friction of haptic interface.
Proceedings of the 2010 IEEE Haptics Symposium, 2010

Intent-leveraged optimization of analog circuits via homotopy.
Proceedings of the Design, Automation and Test in Europe, 2010

An efficient test vector generation for checking analog/mixed-signal functional models.
Proceedings of the 47th Design Automation Conference, 2010

Equalizer design and performance trade-offs in ADC-based serial links.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Simulation and Analysis of Random Decision Errors in Clocked Comparators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Design Optimization of On-Chip Inductive Peaking Structures for 0.13-μm CMOS 40-Gb/s Transmitter Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

On-Chip Measurement of Jitter Transfer and Supply Sensitivity of PLL/DLLs.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Adaptive-Bandwidth Phase-Locked Loop With Continuous Background Frequency Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Accurate and Efficient CPU/GPU-Based 3-DOF Haptic Rendering of Complex Static Virtual Environments.
Presence Teleoperators Virtual Environ., 2009

A Fully Integrated 0.13-µm CMOS 40-Gb/s Serial Link Transceiver.
IEEE J. Solid State Circuits, 2009

Energy-bounding algorithm for stable haptic interaction and bilateral teleoperation.
Proceedings of the World Haptics 2009, 2009

An energy bounding approach for directional transparency in multiple degree-of-freedom haptic interaction.
Proceedings of the World Haptics 2009, 2009

Stochastic steady-state and AC analyses of mixed-signal systems.
Proceedings of the 46th Design Automation Conference, 2009

Leveraging designer's intent: A path toward simpler analog CAD tools.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

Mixed-Signal System Verification: A High-Speed Link Example.
Proceedings of the Computer Aided Verification, 21st International Conference, 2009

2008
Impulse sensitivity function analysis of periodic circuits.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Characterization of random decision errors in clocked comparators.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A Single-Pair Serial Link for Mobile Displays With Clock Edge Modulation Scheme.
IEEE J. Solid State Circuits, 2007

Variable domain transformation for linear PAC analysis of mixed-signal systems.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-μm CMOS.
IEEE J. Solid State Circuits, 2006

Replica compensated linear regulators for supply-regulated phase-locked loops.
IEEE J. Solid State Circuits, 2006

2005
A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique.
IEEE J. Solid State Circuits, 2005

2003
Design of CMOS adaptive-bandwidth PLL/DLLs: a general approach.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL.
IEEE J. Solid State Circuits, 2003

Multi-gigabit-rate clock and data recovery based on blind oversampling.
IEEE Commun. Mag., 2003

2002
An efficient digital sliding controller for adaptive power-supply regulation.
IEEE J. Solid State Circuits, 2002

2000
A variable-frequency parallel I/O interface with adaptive power-supply regulation.
IEEE J. Solid State Circuits, 2000


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